Sofics – Solutions for ICs – on-chip ESD protection, custom/specialty I/O and PHY circuits

Why schematic-correct designs fail at advanced nodes: Siemens EDA and Sofics Webinar 2026

Siemens EDA and Sofics Webinar 2026 Introduction Getting a design to pass simulation at schematic level is only half the job. We joined Siemens EDA, through EDA Solutions in June 2026 for a webinar on why a design that looks perfectly correct on schematic can still fail once it’s extracted from layout, and what that…

Radiation-Hardened by Design: Building Interfaces for Space and Nuclear on TSMC CMOS

Prepared by Emil Hågan and Wouter Faelens (Sofics), in collaboration with Magics Technologies. Presented at the 2025 TSMC OIP Forum. Most chips live an easy life with room temperature, clean power and a steady supply. The chips in this article do not. They sit inside nuclear reactors, ride on satellites and work next to particle…

“Ensuring reliability in Advanced IC design” – Siemens EDA and Sofics Webinar 2025

Introduction To complete our task as engineers we rely on the tools we use. We collaborated with Siemens EDA solutions back in 2025 on a webinar about how we use their tools to develop our designs and layouts. In this webinar, which is available here https://www.eda-solutions.com/resources/ensuring-reliability-in-advanced-ic-design-webinar/, Khalid presented how the Siemens EDA tools can support…

Breaking the Bandwidth Barrier: Enabling Celestial AI’s Photonic Fabric™ with Custom ESD IP on TSMC’s 5nm Platform

As AI workloads scale exponentially, bandwidth has become the new bottleneck. This article explores how Celestial AI’s Photonic Fabric™ redefines interconnect performance, and how Sofics’ low-cap ESD and power clamp IP enabled its integration on TSMC’s 5nm platform. A deep dive into real silicon innovation from the TSMC OIP Forum stage.

EOS protection characterization using Long-Pulse TLP

EOS, or Electrical Overstress, is a significant factor in IC reliability. Sometimes, IC interfaces and/or power pads are subjected to voltage/current levels beyond the absolute maximum rating. Sources claim that more than 40% of the field failures in electronic products are related to EOS. Unlike Electrostatic Discharge (ESD), which is a short and sudden event,…

ESD Protection for a High Voltage Tolerant Driver Circuit in 4nm FinFET Technology

As semiconductor technology scales down, the maximum tolerated voltage by the transistors is no longer sufficiently high to accommodate (older) I/O-standards. For instance, in 4nm FinFET technology, the maximum tolerated voltage during normal operation is limited to 1.2V, which does not support common bus standards like 1.8V.

In this article, we present an Overvoltage tolerant…

Keep your friends close but your AI closer

As AI rapidly becomes part of the modern workplace, companies face a fundamental question: should we use public AI services or run AI models on our own infrastructure? This blog post shares our own evaluation approach with real use cases.

Why ESD Co-Design is Essential for Next-Gen ICs

In the fast-moving world of semiconductor design, electrical overstress (EOS) and electrostatic discharge (ESD) remain stubborn challenges. As silicon nodes shrink and performance demands rise, traditional approaches to ESD protection are reaching their limits. The classic model of sequential ESD design—where the I/O or PHY circuitry is finalized before protection is added—is not only outdated,…

GPIO Solutions for CERN’s Radiation-Hardened Applications

For over a decade, Sofics has collaborated with CERN, the European Organization for Nuclear Research. Sofics has delivered advanced GPIO cells tailored for radiation-hardened applications, supporting CERN’s groundbreaking particle physics experiments.

Not all overvoltage tolerant GPIOs are the same

For some IC products the foundry provided GPIO libraries cover all the required I/O needs. However for several application types IC designers have requirements that cannot be met with those generic I/O cells. One of those requirements is the request for ‘overvoltage tolerant I/Os’. However there are a number of different cases, with distinct requirements…

Overvoltage tolerant receiver structures

In general, the input section of a digital I/O can be a relatively simple circuit, such as an inverter. Furthermore, these circuits exhibit excellent performance regarding input impedance (which is exceptionally high), power consumption (negligible under steady-state conditions), and speed (extremely fast).

Under certain conditions, it is necessary that an input section is OverVoltage Tolerant…

Typical SOA violations in a stacked driver

A typical overvoltage tolerant (OVT) driver is a stack of two devices. The first device connected to rail is used to switch the I/O voltage, while the second device connected to pad is used to protect against the high voltage.

In this article, we will have a look at a couple of possible SOA (safe…

Types of overvoltage tolerant I/O

At Sofics, we specialize in overvoltage-tolerant I/O’s. However, the term “overvoltage tolerant I/O” can mean different things to different people. For some, it might simply refer to a circuit that can withstand high voltages. Others may interpret it as a voltage higher than what the technology permits. Still, others might equate it to an open-drain…

I/O specs explained

Similar to every electrical component, a GPIO is built to certain specifications. The type of specifications are universal across every GPIO, and are thus important to understand in order to understand what you are using.

We will start by dividing the specifications three major categories. We have the output path (driver), input path (receiver) and…

Building a Sustainable Future: Sofics and ONiO Collaborate on Battery-Free Devices

Learn how Sofics’ ultra-low leakage ESD protection IP is enabling ONiO’s groundbreaking battery-free MCU, paving the way for sustainable, energy-efficient IoT solutions