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Protecting die-2-die interfaces…

At Sofics we get a lot of questions about the required ESD robustness for the die-2-die (D2D) interfaces between chiplets in a package. People wonder how to select the right ESD standard and what robustness level they need to design for. Sofics has supported several chiplet projects for AI, data center communication applications recently.

ESD basic: Silicon Control Rectifier (SCR)

SCR intro: Silicon-controlled rectifiers (SCRs) are interesting devices that can be used for on-chip ESD protection, if (and only if) they are properly designed and biased. SCRs are used for high-speed/RF or low-capacitance, small area/high-performance ESD solutions in all CMOS technologies, including SOI and FinFET (down to 3nm today). SCR operation: Figure 1 introduces the…

ggNMOS (grounded-gated NMOS)

ggNMOS intro: For decades, a traditional workhorse device for ESD protection for standard applications in CMOS technology has been the grounded-gate NMOS device (ggNMOS). Nevertheless, we have been explaining the operation of this device countless times, including as recently as 3 weeks ago. So, it is time for a short blog article. The schematic of…

Let’s talk about 2023

Sofics’ CEO outlook for 2023… 2023 will be a year of opportunity to invest in our readiness to grow and flourish in 2024. Whatever your semiconductor business, your key assets: team, skills, technology, processes, and reputation, should not go to waste.

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About SOFICS

Sofics is a foundry-independent semiconductor IP provider. In the last 20 years our engineers supported 100+ fabless companies worldwide with on-chip ESD protection, custom/specialty Analog I/O’s and PHY’s on multiple foundries.

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Tutorial Videos
TUTORIAL: DTSCR
TUTORIAL: TLP
TUTORIAL: VF-TLP
TUTORIAL: LOCAL ESD PROTECTION FOR ANALOG IOs

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