on-chip ESD protection, custom/specialty I/O and PHY circuits
Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions.
We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.
Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
More and more companies are turning to advanced semiconductor packaging. This trend has an effect on ESD protection. Earlier in 2021, Sofics submited a paper for the IP-SOC USA conference about ESD protection for 2.5D and 3D packaging. The abstract, the presentation and video are available here.
A growing number of semiconductor applications are turning to 2.5D and 3D integration. Integrating multiple dies in a single package can reduce total power consumption, reduce required PCB area, enhance performance and it can speed up development cycles.
It is important to consider Electrostatic Discharge (ESD) protection early in the design phase. The 2.5D and 3D hybrid integration introduces new ESD challenges but also opportunities.
Datacenter companies are turning to optical communication to increase the bandwidth of communication between servers. Thanks to several breakthroughs in the last decades the so-called Silicon Photonics solutions promise higher communication speed and lower power consumption at a reduced cost. This article discusses the need for custom ESD protection for optical communication interfaces.
High performance applications like server CPUs in a datacenter are typically made using the most advanced semiconductor processing technology. The latest process node provides benefits like lower power dissipation, higher transistor density and higher processing speed. However, IC designers developing chips in such advanced processes need to take extra efforts to ensure the chips areContinue reading “ESD protection for FinFET processes”
Sofics’ 2017 EOS/ESD publication. This paper presents a novel approach to reduce the parasitic capacitive loading of RF and high speed digital interfaces by up to 35%. Unlike in the classic dual diode protection, both junctions connected to the pad are used in every stress combination.
SOFICS - Solutions for ICs