For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below).
However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.
Category Archives: ESD testing
Applying System level ESD (IEC 61000-4-2) stress on ICs
Despite the fact that IEC 61000-4-2 is a standard created for system level ESD stress it is frequently used for stand alone integrated circuits. The test approach for chips is not defined nor standardized for this requirement so it is important to have a discussion on the test conditions and acceptance criteria. This article outlines 3 aspects that need to be considered if on-chip ESD protection needs to withstand the IEC 61000-4-2 stress
Transmission Line Pulse (TLP) test system
To prevent failures during production, assembly and test, IC designers include on-chip Electrostatic Discharge (ESD) protection structures at the interfaces of their Integrated Circuits. This article discusses the main measurement technique, used by ESD experts to characterize ESD protection structures as well as the intrinsic process technology robustness or weakness.
CDM robustness of SCR protection devices
We often get the question: what is the CDM robustness of your ESD protection circuit? Though the question is clear, it is very hard to formulate a meaningful answer. CDM qualifies the performance of an IC or die in a specific package. Nevertheless, one expects an answer for the ESD circuit expressed in Volts.
This article discusses how VF-TLP analysis can be used to assess the CDM current capability of ESD devices.
SOFICS - Solutions for ICs 