At Sofics we get a lot of questions about the required ESD robustness for the die-2-die (D2D) interfaces between chiplets in a package. People wonder how to select the right ESD standard and what robustness level they need to design for. Sofics has supported several chiplet projects for AI, data center communication applications recently.
Category Archives: SerDes
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
Sofics’ 2021 IEDS publication.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration
Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
ESD protection of interfaces with thin gate oxide transistors
How do you protect chip interfaces that require thin gate (core) transistors in advanced CMOS, SOI of FinFET processes? How do you ensure sufficient ESD robustness? Conventional ESD protection is not sufficient. Discover the background for that and a solution as well in this article. The answer is found in a strategy of local clamping with power-efficient devices.
ESD protection for 2.5D and 3D packages
A growing number of semiconductor applications are turning to 2.5D and 3D integration. Integrating multiple dies in a single package can reduce total power consumption, reduce required PCB area, enhance performance and it can speed up development cycles.
It is important to consider Electrostatic Discharge (ESD) protection early in the design phase. The 2.5D and 3D hybrid integration introduces new ESD challenges but also opportunities.
Optical communication also requires ESD protection
Datacenter companies are turning to optical communication to increase the bandwidth of communication between servers. Thanks to several breakthroughs in the last decades the so-called Silicon Photonics solutions promise higher communication speed and lower power consumption at a reduced cost. This article discusses the need for custom ESD protection for optical communication interfaces.
ESD protection for FinFET processes
High performance applications like server CPUs in a datacenter are typically made using the most advanced semiconductor processing technology. The latest process node provides benefits like lower power dissipation, higher transistor density and higher processing speed. However, IC designers developing chips in such advanced processes need to take extra efforts to ensure the chips areContinue reading “ESD protection for FinFET processes”
Local ESD protection in analog IOs
The most common ESD protection for I/Os consist of two diodes. To cover all the different stress combinations a rail clamp is required. In this article we discuss another option. For many interfaces a local ESD protection clamp is actually a better option.
Low Capacitive Dual Bipolar ESD Protection
Sofics’ 2017 EOS/ESD publication. This paper presents a novel approach to reduce the parasitic capacitive loading of RF and high speed digital interfaces by up to 35%. Unlike in the classic dual diode protection, both junctions connected to the pad are used in every stress combination.
SOFICS - Solutions for ICs 