Sofics’ 2021 IEDS publication.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
Category Archives: ESD devices
Selecting custom ESD IP for your next IC
Fabless semiconductor companies usually use third-party IP blocks when developing ICs. An important IP is on-chip ESD protection. Caution must be exercised in choosing the right ESD IP to avoid patent infringement and inefficient ESD clamps.
Thomas Ako made a presentation about the IP selection process on the 2021 IP-SOC event in Grenoble in December 2021.
Introduction: ESD protection concepts for I/Os
There are many different approaches to ensure effective ESD protection for integrated circuits. It is important to select the right approach for each interface and power domain. This article outlines the main options for Interface protection.
Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes
Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions.
We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.
Time to say farewell to the snapback ggNMOS for ESD protection
For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below).
However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.
Introduction about ESD protection: basic concepts to advanced applications
Koen Decock, ESD design specialist at Sofics, made a presentation for a full auditorium, organized by the local IEEE SSCS student chapter in Leuven. He talked about on-chip ESD protection, from the basic concepts to the more advanced applications.
ESD clamps for high voltage, BCD processes
Some applications really need high voltage interfaces and circuits. Think about power management and power conversion chips, automotive electronics for engine control, LCD or OLED display driver chips, motor driver electronics and industrial applications. These high voltage applications require other ESD protection clamps compared to the clamps used for protection of low voltage circuits.
Sofics has been involved in a number of chip projects that require custom ESD clamps for high voltage interfaces.
Optimized IP for GF’s 22nm FDX technology
The 22nm FDX process from GlobalFoundries is a great technology for various applications including low-power IoT on the edge, high-bandwidth 5G mmWave devices and automotive products, Since its market introduction, the SOI process technology receives a lot of attention because it combines unique features in one platform.
Sofics supported a number of products on the 22FDX technology like low-leakage protection for IoT and Bluetooth applications.
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
ESD protection for 8.5 GHz LNA in 90nm
This article provides information about an SCR based ESD protection clamp for RF circuits validated in TSMC 90nm CMOS technology. The ESD protection clamp described has excellent figures of merit: Due to the low parasitic capacitance, low leakage and high Q-factor the influence on the RF performance is limited.
SOFICS - Solutions for ICs 