Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Sofics’ 2021 IEDS publication.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

Solving the problems with traditional Silicon Controlled Rectifier (SCR) approaches for ESD

Sofics’ 2008 RCJ publication.

The Silicon Controlled Rectifier (‘SCR’) is widely used for ESD protection due to its superior performance and clamping capabilities. However, many believe that SCR based ESD protection is prone to latch-up, competitive triggering, long development cycles and slow trigger speed. This paper provides an overview of the problems and corresponding design solutions available.