For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below).
However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.
on-chip ESD protection, custom/specialty Analog I/O’s and PHY’s
For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below).
However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.
Some applications really need high voltage interfaces and circuits. Think about power management and power conversion chips, automotive electronics for engine control, LCD or OLED display driver chips, motor driver electronics and industrial applications. These high voltage applications require other ESD protection clamps compared to the clamps used for protection of low voltage circuits.
Sofics has been involved in a number of chip projects that require custom ESD clamps for high voltage interfaces.