In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution.
With its local ESD clamp approach, Sofics provides the best solution to protect those high-speed chip interfaces against Electrostatic Discharge events.
Fabless semiconductor companies usually use third-party IP blocks when developing ICs. An important IP is on-chip ESD protection. Caution must be exercised in choosing the right ESD IP to avoid patent infringement and inefficient ESD clamps.
Thomas Ako made a presentation about the IP selection process on the 2021 IP-SOC event in Grenoble in December 2021.
There are many different approaches to ensure effective ESD protection for integrated circuits. It is important to select the right approach for each interface and power domain. This article outlines the main options for Interface protection.
Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions.
We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.
For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below).
However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.
Space applications require custom I/O and ESD protection solutions. Sofics proprietary ESD technology has been used for a number of aerospace projects. Our engineers delivered custom rad-hard ESD devices for TSMC 28nm, 65nm and 130nm CMOS technologies. The cells enable low power design in an extended temperature range. Different concepts are used to enable cold-spare interfaces. Low voltage triggered solutions are available for protection of thin oxide interface circuits.
Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.
Koen Decock, ESD design specialist at Sofics, made a presentation for a full auditorium, organized by the local IEEE SSCS student chapter in Leuven. He talked about on-chip ESD protection, from the basic concepts to the more advanced applications.
Some applications really need high voltage interfaces and circuits. Think about power management and power conversion chips, automotive electronics for engine control, LCD or OLED display driver chips, motor driver electronics and industrial applications. These high voltage applications require other ESD protection clamps compared to the clamps used for protection of low voltage circuits.
Sofics has been involved in a number of chip projects that require custom ESD clamps for high voltage interfaces.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.