Protection of CMOS output drivers

Every computer chip needs on-chip ESD protection at its interfaces. Integrated circuits have different kinds of interfaces. This article discusses approaches to protect output drivers. This article compares different options for output drivers, focused on the NMOS transistor because that is the most sensitive part and is easily damaged during ESD stress.

ESD protection for SOI technology

SOI technology introduces several challenges for the ESD designer. This article provided more background and example data on these issues. Fortunately, there are several ways to overcome those challenges. Sofics has supported IC companies with novel ESD concepts that improve IC performance and increase the ESD robustness.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 2)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 1)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

CDM robustness of SCR protection devices

We often get the question: what is the CDM robustness of your ESD protection circuit? Though the question is clear, it is very hard to formulate a meaningful answer. CDM qualifies the performance of an IC or die in a specific package. Nevertheless, one expects an answer for the ESD circuit expressed in Volts.

This article discusses how VF-TLP analysis can be used to assess the CDM current capability of ESD devices.

Adapting Diode triggered SCRs (part 2)

In this article, I wish to introduce you to how we can use diode triggered silicon controlled rectifiers (DTSCRs) for on-chip ESD protection. I will explain how its 3 main parameters – trigger voltage, holding voltage and failure current – can be tuned in order to protect ICs with very different characteristics.

Diode triggered SCRs for ESD protection in CMOS ICs (part 1)

A specific case of an SCR-based solution which can be used to develop a wide range of on-chip ESD protection circuits is the diode triggered SCR (DTSCR). As its name implies, a DTSCR is constructed by combining an SCR with diodes to form a versatile circuit whose properties can be tuned at will to suit the requirements of the IC/interface which needs to be protected.

Latch-up in CMOS circuits: threat or opportunity (part 2)

Latch-up refers to unwanted short circuits which can occur in an integrated circuit whereby the power supply is inadvertently connected to the ground. In the first part (threat) of the article the focus was on the threat of latch-up and different ways to prevent it. In this part (opportunity) we discuss how (parasitic) SCR devices can be used in a positive way.