Due to the semiconductor shortage in 2021 everyone realized that cars these days integrate a lot of electronics. The average number of computer chips per car has increased a lot in the last decade.
It is clear that the new applications require high-speed interconnects that are not possible with the initial, low-speed interface types. But there is also innovation possible for the old interface types like LIN/CAN by combining it together with other IP blocks on a single die.
EOS, or Electrical Overstress, is any electrical stress that exceeds any of the specified absolute maximum ratings (AMR) of a product.
It is important to discuss because many products are damaged this way.
This article includes case studies and 3 approaches to handle those requests.
In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution.
With its local ESD clamp approach, Sofics provides the best solution to protect those high-speed chip interfaces against Electrostatic Discharge events.
Some applications really need high voltage interfaces and circuits. Think about power management and power conversion chips, automotive electronics for engine control, LCD or OLED display driver chips, motor driver electronics and industrial applications. These high voltage applications require other ESD protection clamps compared to the clamps used for protection of low voltage circuits.
Sofics has been involved in a number of chip projects that require custom ESD clamps for high voltage interfaces.
Despite the fact that IEC 61000-4-2 is a standard created for system level ESD stress it is frequently used for stand alone integrated circuits. The test approach for chips is not defined nor standardized for this requirement so it is important to have a discussion on the test conditions and acceptance criteria. This article outlines 3 aspects that need to be considered if on-chip ESD protection needs to withstand the IEC 61000-4-2 stress