Latch-up immunity – SOFICS – Solutions for ICs

Latch-up in CMOS circuits: threat or opportunity (part 2)

Latch-up refers to unwanted short circuits which can occur in an integrated circuit whereby the power supply is inadvertently connected to the ground. In the first part (threat) of the article the focus was on the threat of latch-up and different ways to prevent it. In this part (opportunity) we discuss how (parasitic) SCR devices can be used in a positive way.

Latch-up in CMOS circuits: threat or opportunity (part 1)

In the first article about Latch-up, Thomas discusses the mechanism of the positive feedback loop between parasitic bipolar devices inside a CMOS inverter stage. He summarizes different causes and also provides ways to prevent latch-up threats.

Solving the problems with traditional Silicon Controlled Rectifier (SCR) approaches for ESD

Sofics’ 2008 RCJ publication.

The Silicon Controlled Rectifier (‘SCR’) is widely used for ESD protection due to its superior performance and clamping capabilities. However, many believe that SCR based ESD protection is prone to latch-up, competitive triggering, long development cycles and slow trigger speed. This paper provides an overview of the problems and corresponding design solutions available.