Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

ESD protection for 2.5D and 3D packages

More and more companies are turning to advanced semiconductor packaging. This trend has an effect on ESD protection. Earlier in 2021, Sofics submited a paper for the IP-SOC USA conference about ESD protection for 2.5D and 3D packaging. The abstract, the presentation and video are available here.

ESD protection of interfaces with thin gate oxide transistors

How do you protect chip interfaces that require thin gate (core) transistors in advanced CMOS, SOI of FinFET processes? How do you ensure sufficient ESD robustness? Conventional ESD protection is not sufficient. Discover the background for that and a solution as well in this article. The answer is found in a strategy of local clamping with power-efficient devices.

Local ESD protection in analog IOs

The most common ESD protection for I/Os consist of two diodes. To cover all the different stress combinations a rail clamp is required. In this article we discuss another option. For many interfaces a local ESD protection clamp is actually a better option.

Diode triggered SCRs for ESD protection in CMOS ICs (part 1)

A specific case of an SCR-based solution which can be used to develop a wide range of on-chip ESD protection circuits is the diode triggered SCR (DTSCR). As its name implies, a DTSCR is constructed by combining an SCR with diodes to form a versatile circuit whose properties can be tuned at will to suit the requirements of the IC/interface which needs to be protected.