SCR intro: Silicon-controlled rectifiers (SCRs) are interesting devices that can be used for on-chip ESD protection, if (and only if) they are properly designed and biased. SCRs are used for high-speed/RF or low-capacitance, small area/high-performance ESD solutions in all CMOS technologies, including SOI and FinFET (down to 3nm today). SCR operation: Figure 1 introduces theContinue reading “ESD basic: Silicon Control Rectifier (SCR)”
Tag Archives: Local clamp
ggNMOS (grounded-gated NMOS)
ggNMOS intro: For decades, a traditional workhorse device for ESD protection for standard applications in CMOS technology has been the grounded-gate NMOS device (ggNMOS). Nevertheless, we have been explaining the operation of this device countless times, including as recently as 3 weeks ago. So, it is time for a short blog article. The schematic ofContinue reading “ggNMOS (grounded-gated NMOS)”
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
Sofics’ 2021 IEDS publication.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
Selecting optimized ESD protection for CMOS image sensors
Today, you can find CMOS image sensors almost everywhere in consumer, automotive, health and security applications. There has been a lot of innovation to enable demanding requirements.
The article provides a summary about the 3 main aspects that IC designers need to consider when selecting the ESD protection clamps for their image sensor projects.
3 approaches to handle EOS ‘requirements’
EOS, or Electrical Overstress, is any electrical stress that exceeds any of the specified absolute maximum ratings (AMR) of a product.
It is important to discuss because many products are damaged this way.
This article includes case studies and 3 approaches to handle those requests.
Optimized on-chip ESD protection to enable high-speed Ethernet in cars.
In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution.
With its local ESD clamp approach, Sofics provides the best solution to protect those high-speed chip interfaces against Electrostatic Discharge events.
Introduction: ESD protection concepts for I/Os
There are many different approaches to ensure effective ESD protection for integrated circuits. It is important to select the right approach for each interface and power domain. This article outlines the main options for Interface protection.
Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes
Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions.
We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
Applying System level ESD (IEC 61000-4-2) stress on ICs
Despite the fact that IEC 61000-4-2 is a standard created for system level ESD stress it is frequently used for stand alone integrated circuits. The test approach for chips is not defined nor standardized for this requirement so it is important to have a discussion on the test conditions and acceptance criteria. This article outlines 3 aspects that need to be considered if on-chip ESD protection needs to withstand the IEC 61000-4-2 stress
SOFICS - Solutions for ICs 