Fabless semiconductor companies usually use third-party IP blocks when developing ICs. An important IP is on-chip ESD protection. Caution must be exercised in choosing the right ESD IP to avoid patent infringement and inefficient ESD clamps.
Thomas Ako made a presentation about the IP selection process on the 2021 IP-SOC event in Grenoble in December 2021.
It’s Christmas 2021. The semiconductor industry is flooded with income: all fabs run at or above maximum capacity, volumes are in short supply while prices of wafers and ICs are floating up. Electronics are everywhere in our lock-down offices and private homes, and in many other systems and services that all of us use (almost) every day.
Sofics’ CEO outlook for 2022…
How do you protect chip interfaces that require thin gate (core) transistors in advanced CMOS, SOI of FinFET processes? How do you ensure sufficient ESD robustness? Conventional ESD protection is not sufficient. Discover the background for that and a solution as well in this article. The answer is found in a strategy of local clamping with power-efficient devices.
This interview was held with Koen Verhaege, CEO of Sofics, June 2020Link to article: https://anysilicon.com/ceo-talk-koen-verhaege-sofics/ Tell me a bit about your background? How did you first get started with your company? I graduated from the University of Leuven, Belgium, with a degree in microelectronics in 1990 and started my professional career at IMEC in theContinue reading “ANYSILICON CEO TALK”