To prevent failures during production, assembly and test, IC designers include on-chip Electrostatic Discharge (ESD) protection structures at the interfaces of their Integrated Circuits. This article discusses the main measurement technique, used by ESD experts to characterize ESD protection structures as well as the intrinsic process technology robustness or weakness.
We often get the question: what is the CDM robustness of your ESD protection circuit? Though the question is clear, it is very hard to formulate a meaningful answer. CDM qualifies the performance of an IC or die in a specific package. Nevertheless, one expects an answer for the ESD circuit expressed in Volts.
This article discusses how VF-TLP analysis can be used to assess the CDM current capability of ESD devices.