on-chip ESD protection, custom/specialty I/O and PHY circuits
Due to the semiconductor shortage in 2021 everyone realized that cars these days integrate a lot of electronics. The average number of computer chips per car has increased a lot in the last decade.
It is clear that the new applications require high-speed interconnects that are not possible with the initial, low-speed interface types. But there is also innovation possible for the old interface types like LIN/CAN by combining it together with other IP blocks on a single die.
We frequently get questions about the applicability of our ESD and I/O solution IP for space applications. Semiconductor devices that are used at high elevation or in space need special attention during the design phase. Sofics technology has been used for a number of aerospace projects. In this article we provide more background and some example cases.
Latch-up refers to unwanted short circuits which can occur in an integrated circuit whereby the power supply is inadvertently connected to the ground. In the first part (threat) of the article the focus was on the threat of latch-up and different ways to prevent it. In this part (opportunity) we discuss how (parasitic) SCR devices can be used in a positive way.
In the first article about Latch-up, Thomas discusses the mechanism of the positive feedback loop between parasitic bipolar devices inside a CMOS inverter stage. He summarizes different causes and also provides ways to prevent latch-up threats.
Sofics’ 2008 RCJ publication.
The Silicon Controlled Rectifier (‘SCR’) is widely used for ESD protection due to its superior performance and clamping capabilities. However, many believe that SCR based ESD protection is prone to latch-up, competitive triggering, long development cycles and slow trigger speed. This paper provides an overview of the problems and corresponding design solutions available.
SOFICS - Solutions for ICs