Optimized on-chip ESD protection to enable high-speed Ethernet in cars.

In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution.

With its local ESD clamp approach, Sofics provides the best solution to protect those high-speed chip interfaces against Electrostatic Discharge events.

Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes

Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions.

We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.

Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration

Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 2)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 1)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

ESD protection of interfaces with thin gate oxide transistors

How do you protect chip interfaces that require thin gate (core) transistors in advanced CMOS, SOI of FinFET processes? How do you ensure sufficient ESD robustness? Conventional ESD protection is not sufficient. Discover the background for that and a solution as well in this article. The answer is found in a strategy of local clamping with power-efficient devices.

ESD protection for FinFET processes

High performance applications like server CPUs in a datacenter are typically made using the most advanced semiconductor processing technology. The latest process node provides benefits like lower power dissipation, higher transistor density and higher processing speed. However, IC designers developing chips in such advanced processes need to take extra efforts to ensure the chips areContinue reading “ESD protection for FinFET processes”