FinFET – SOFICS – Solutions for ICs

Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Sofics’ 2021 IEDS publication.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

Optimized on-chip ESD protection to enable high-speed Ethernet in cars.

In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution.

With its local ESD clamp approach, Sofics provides the best solution to protect those high-speed chip interfaces against Electrostatic Discharge events.

Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes

Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions.

We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.

Time to say farewell to the snapback ggNMOS for ESD protection

For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below).

However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.

Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration

Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.

Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

ESD protection for 2.5D and 3D packages

More and more companies are turning to advanced semiconductor packaging. This trend has an effect on ESD protection. Earlier in 2021, Sofics submited a paper for the IP-SOC USA conference about ESD protection for 2.5D and 3D packaging. The abstract, the presentation and video are available here.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 2)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 1)

CDM robustness of SCR protection devices

We often get the question: what is the CDM robustness of your ESD protection circuit? Though the question is clear, it is very hard to formulate a meaningful answer. CDM qualifies the performance of an IC or die in a specific package. Nevertheless, one expects an answer for the ESD circuit expressed in Volts.

This article discusses how VF-TLP analysis can be used to assess the CDM current capability of ESD devices.