Sofics’ 2021 IEDS publication.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
Category Archives: Wired communication
Selecting optimized ESD protection for CMOS image sensors
Today, you can find CMOS image sensors almost everywhere in consumer, automotive, health and security applications. There has been a lot of innovation to enable demanding requirements.
The article provides a summary about the 3 main aspects that IC designers need to consider when selecting the ESD protection clamps for their image sensor projects.
Optimized on-chip ESD protection to enable high-speed Ethernet in cars.
In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution.
With its local ESD clamp approach, Sofics provides the best solution to protect those high-speed chip interfaces against Electrostatic Discharge events.
Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes
Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions.
We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.
Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration
Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
Applying System level ESD (IEC 61000-4-2) stress on ICs
Despite the fact that IEC 61000-4-2 is a standard created for system level ESD stress it is frequently used for stand alone integrated circuits. The test approach for chips is not defined nor standardized for this requirement so it is important to have a discussion on the test conditions and acceptance criteria. This article outlines 3 aspects that need to be considered if on-chip ESD protection needs to withstand the IEC 61000-4-2 stress
ESD protection for 2.5D and 3D packages
A growing number of semiconductor applications are turning to 2.5D and 3D integration. Integrating multiple dies in a single package can reduce total power consumption, reduce required PCB area, enhance performance and it can speed up development cycles.
It is important to consider Electrostatic Discharge (ESD) protection early in the design phase. The 2.5D and 3D hybrid integration introduces new ESD challenges but also opportunities.
ESD protection for FinFET processes
High performance applications like server CPUs in a datacenter are typically made using the most advanced semiconductor processing technology. The latest process node provides benefits like lower power dissipation, higher transistor density and higher processing speed. However, IC designers developing chips in such advanced processes need to take extra efforts to ensure the chips areContinue reading “ESD protection for FinFET processes”
Low Capacitive Dual Bipolar ESD Protection
Sofics’ 2017 EOS/ESD publication. This paper presents a novel approach to reduce the parasitic capacitive loading of RF and high speed digital interfaces by up to 35%. Unlike in the classic dual diode protection, both junctions connected to the pad are used in every stress combination.
SOFICS - Solutions for ICs 