Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

ESD protection for 8.5 GHz LNA in 90nm

This article provides information about an SCR based ESD protection clamp for RF circuits validated in TSMC 90nm CMOS technology. The ESD protection clamp described has excellent figures of merit: Due to the low parasitic capacitance, low leakage and high Q-factor the influence on the RF performance is limited.

Optical communication also requires ESD protection

Datacenter companies are turning to optical communication to increase the bandwidth of communication between servers. Thanks to several breakthroughs in the last decades the so-called Silicon Photonics solutions promise higher communication speed and lower power consumption at a reduced cost. This article discusses the need for custom ESD protection for optical communication interfaces.