Sofics’ 2021 IEDS publication.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
Category Archives: Low capacitance ESD
Selecting optimized ESD protection for CMOS image sensors
Today, you can find CMOS image sensors almost everywhere in consumer, automotive, health and security applications. There has been a lot of innovation to enable demanding requirements.
The article provides a summary about the 3 main aspects that IC designers need to consider when selecting the ESD protection clamps for their image sensor projects.
Optimized on-chip ESD protection to enable high-speed Ethernet in cars.
In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution.
With its local ESD clamp approach, Sofics provides the best solution to protect those high-speed chip interfaces against Electrostatic Discharge events.
Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes
Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions.
We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.
Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration
Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
ESD protection for 8.5 GHz LNA in 90nm
This article provides information about an SCR based ESD protection clamp for RF circuits validated in TSMC 90nm CMOS technology. The ESD protection clamp described has excellent figures of merit: Due to the low parasitic capacitance, low leakage and high Q-factor the influence on the RF performance is limited.
ESD protection for 2.5D and 3D packages
More and more companies are turning to advanced semiconductor packaging. This trend has an effect on ESD protection. Earlier in 2021, Sofics submited a paper for the IP-SOC USA conference about ESD protection for 2.5D and 3D packaging. The abstract, the presentation and video are available here.
ESD protection for 2.5D and 3D packages
A growing number of semiconductor applications are turning to 2.5D and 3D integration. Integrating multiple dies in a single package can reduce total power consumption, reduce required PCB area, enhance performance and it can speed up development cycles.
It is important to consider Electrostatic Discharge (ESD) protection early in the design phase. The 2.5D and 3D hybrid integration introduces new ESD challenges but also opportunities.
Optical communication also requires ESD protection
Datacenter companies are turning to optical communication to increase the bandwidth of communication between servers. Thanks to several breakthroughs in the last decades the so-called Silicon Photonics solutions promise higher communication speed and lower power consumption at a reduced cost. This article discusses the need for custom ESD protection for optical communication interfaces.
SOFICS - Solutions for ICs 