3 approaches to handle EOS ‘requirements’

EOS, or Electrical Overstress, is any electrical stress that exceeds any of the specified absolute maximum ratings (AMR) of a product.

It is important to discuss because many products are damaged this way.

This article includes case studies and 3 approaches to handle those requests.

Optimized on-chip ESD protection to enable high-speed Ethernet in cars.

In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution.

With its local ESD clamp approach, Sofics provides the best solution to protect those high-speed chip interfaces against Electrostatic Discharge events.

Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes

Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions.

We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.

Time to say farewell to the snapback ggNMOS for ESD protection

For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below).

However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.

ESD protection solutions for space applications

Space applications require custom I/O and ESD protection solutions. Sofics proprietary ESD technology has been used for a number of aerospace projects. Our engineers delivered custom rad-hard ESD devices for TSMC 28nm, 65nm and 130nm CMOS technologies. The cells enable low power design in an extended temperature range. Different concepts are used to enable cold-spare interfaces. Low voltage triggered solutions are available for protection of thin oxide interface circuits.

Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration

Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.

Optimized IP for GF’s 22nm FDX technology

The 22nm FDX process from GlobalFoundries is a great technology for various applications including low-power IoT on the edge, high-bandwidth 5G mmWave devices and automotive products, Since its market introduction, the SOI process technology receives a lot of attention because it combines unique features in one platform.

Sofics supported a number of products on the 22FDX technology like low-leakage protection for IoT and Bluetooth applications.

Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

ESD protection for Internet-of-Things (IoT)

What is the right ESD requirement for IoT applications? The internet of Things circuits are used in new environments. It is not possible to use the same reliability approaches for all the different applications. Sofics’ CEO Koen Verhaege presented an overview and different cases.

ESD protection for 8.5 GHz LNA in 90nm

This article provides information about an SCR based ESD protection clamp for RF circuits validated in TSMC 90nm CMOS technology. The ESD protection clamp described has excellent figures of merit: Due to the low parasitic capacitance, low leakage and high Q-factor the influence on the RF performance is limited.