SOI – SOFICS – Solutions for ICs

Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Sofics’ 2021 IEDS publication.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

Optimized IP for GF’s 22nm FDX technology

The 22nm FDX process from GlobalFoundries is a great technology for various applications including low-power IoT on the edge, high-bandwidth 5G mmWave devices and automotive products, Since its market introduction, the SOI process technology receives a lot of attention because it combines unique features in one platform.

Sofics supported a number of products on the 22FDX technology like low-leakage protection for IoT and Bluetooth applications.

Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

ESD protection for SOI technology

SOI technology introduces several challenges for the ESD designer. This article provided more background and example data on these issues. Fortunately, there are several ways to overcome those challenges. Sofics has supported IC companies with novel ESD concepts that improve IC performance and increase the ESD robustness.

ESD protection solutions for space applications

We frequently get questions about the applicability of our ESD and I/O solution IP for space applications. Semiconductor devices that are used at high elevation or in space need special attention during the design phase. Sofics technology has been used for a number of aerospace projects. In this article we provide more background and some example cases.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 2)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 1)

CDM robustness of SCR protection devices

We often get the question: what is the CDM robustness of your ESD protection circuit? Though the question is clear, it is very hard to formulate a meaningful answer. CDM qualifies the performance of an IC or die in a specific package. Nevertheless, one expects an answer for the ESD circuit expressed in Volts.

This article discusses how VF-TLP analysis can be used to assess the CDM current capability of ESD devices.

ESD protection of interfaces with thin gate oxide transistors

How do you protect chip interfaces that require thin gate (core) transistors in advanced CMOS, SOI of FinFET processes? How do you ensure sufficient ESD robustness? Conventional ESD protection is not sufficient. Discover the background for that and a solution as well in this article. The answer is found in a strategy of local clamping with power-efficient devices.

Solving the problems with traditional Silicon Controlled Rectifier (SCR) approaches for ESD

Sofics’ 2008 RCJ publication.

The Silicon Controlled Rectifier (‘SCR’) is widely used for ESD protection due to its superior performance and clamping capabilities. However, many believe that SCR based ESD protection is prone to latch-up, competitive triggering, long development cycles and slow trigger speed. This paper provides an overview of the problems and corresponding design solutions available.