Introduction: ESD protection concepts for I/Os

There are many different approaches to ensure effective ESD protection for integrated circuits. It is important to select the right approach for each interface and power domain. This article outlines the main options for Interface protection.

Time to say farewell to the snapback ggNMOS for ESD protection

For many years, IC designers coult count on the snapback behaviour of the ggNMOS device for ESD protection in mature CMOS nodes (180nm and below).

However, for more advanced CMOS, FinFET, SOI and high voltage processes there are serious drawbacks.

Protection of CMOS output drivers

Every computer chip needs on-chip ESD protection at its interfaces. Integrated circuits have different kinds of interfaces. This article discusses approaches to protect output drivers. This article compares different options for output drivers, focused on the NMOS transistor because that is the most sensitive part and is easily damaged during ESD stress.