A recent supply shortage in the semiconductor industry led to temporary closures of car fabrication facilities globally. This clearly shows the increased integration of semiconductors in cars. Since the end of the 60-ies, car makers have used electronics for a growing set of functions. Today, about 10% of the total semiconductor market is related to automotive applications. Electronics are used for diverse reasons including entertainment, engine control, dashboard interaction, safety, preventive maintenance, advanced driver-assistance systems (ADAS),…
In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. While LIN and CAN interface will remain the most used interfaces, more recent applications need (much) faster communication options.
Car makers also need a way to add more electronics without increasing the weight and cost. A standardized, flexible and cost-effective, high-speed communication concept is required.
Automotive ethernet is therefore pushed by many in the industry as the perfect solution.
Automotive electronics have always used more stringent reliability requirements compared to consumer applications. Besides an extended temperature range and much longer product life time, the field failure rate needs to be very low.
Car makers define several high voltage and current test standards for ASICs to emulate the harsh environments. These tests are applied on the electronics before they are integrated. This should ensure that potential issues are caught before the semiconductor devices are integrated in the car.
Electrostatic Discharge Protection (ESD)
Semiconductor devices need to be protected against electrostatic discharge. Wafer fabrication and assembly lines use ESD-control methods to ensure high enough yield. This includes connecting equipment and personnel to ground, using ionizers and dissipative containers.
However, ESD events can also occur during the car assembly and functional use. ECU makers have therefore increased the requirements for some IC interfaces from the traditional 2kV HBM level to e.g. 8kV contacted IEC 61000-4-2, which represents a 12 times higher peak current.
Conventional ESD approach
The typical on-chip ESD concept for high-speed interfaces consists of 2 diodes. IC designers like it because this is easy to implement and adapt, has a small silicon footprint and limit parasitic capacitance.
However the conventional approach is not suitable to protect the most sensitive interface circuits. For instance, in FinFET technology, this approach cannot be used to protect circuits based on thin oxide transistors (more info in another article). Moreover, to increase the ESD robustness of the interface pad (to 8kV contact discharge) the rail clamp also needs to be scaled up.
Local I/O clamp approach
At Sofics we prefer another approach that uses a local ESD clamp within the I/O area. This reduces the dependency of the rail clamp and reduces the voltage drop during ESD stress. It also adds flexibility to locally increase the ESD robustness and enables fail-safe interfaces or higher signal voltage.
The technique has been verified on CMOS (40nm – 22nm) and FinFET (16nm – 5nm) processes and included in 30+ projects for high-speed interfaces like Ethernet. More information about this approach is available in earlier blog articles (link1, link2, link3)
Contact us to discuss your automotive chip project. Sofics can provide ESD protection solutions with low parasitic capacitance and high ESD robustness on most foundry platforms.