When your advanced application needs an interface that uses thin gate (core) transistors, how do you ensure sufficient ESD robustness? For one, the foundry PDK provides a no-answer: one may not use core transistors in the periphery because there is no ESD protection solution.
Discover the background for that and a solution as well in this article. The answer is found in the shrinking ESD design window for ever advancing integrated circuit (IC) production technologies, and a strategy of local clamping with power-efficient devices.
ESD design window (for advanced CMOS)
The ESD design window is the proper and safe operation space for an ESD protection circuit in the IC Current-Voltage working space.
On one side it is limited by the IC operating (supply) voltage: in order to not interfere with the IC normal operation, the ESD protection circuit shall not conduct current in the space between the minimum (typical 0V) and the maximum operating voltage (blue line in Figure 1).
On the other side the protection circuit shall shunt the ESD current and keep the voltage drop below the failure voltage of the protected circuit. In case of a thin gate oxide interface, this may align with the thin gate oxide (ESD/transient) breakdown voltage (red line in Figure 1).
Considering the core transistors and voltage domains in advanced FinFET and FDSOI technology, it follows that the ESD design window for thin gate transistor circuits may be as narrow as 3V only, with a maximum allowable voltage drop during ESD at the protected node (a core transistor circuit) of 4V.
Local clamping strategy
How does one consume a 4V drop under ESD current of at least 1.5A? First, you need a fixed voltage drop of (about) 1V (no ESD current conduction below the supply voltage – the blue line of Figure 1). That leaves you with maximum 3V to shunt 1.5A, hence a total resistance of maximum 2Ohm in your discharge path.
Relying on a diode to the supply (dropping 1V at low current)) and solid supply line clamp (dropping 2V at low current) turns out to be not economically feasible – the device sizes would be too large for the limitation to be applied to the series resistance. That series resistance is located in the diode, the supply clamp and the power/ground line in the discharge path.
A different strategy (see also our article about local ESD clamps – Link) is called for: local clamping to cut out the resistive path to and from the power clamp.
Power efficient local clamps
You almost have your solution! You only need one (bi-directional) clamp that keeps the voltage drop low enough. We recommend carefully engineered SCR based devices – Silicon Controlled Rectifiers. An I-V plot measured by TLP compares such solution (blue line in Figure 3) with a traditional clamp (green line in Figure 3).
If the typical PDK solution is applied for ESD protection of your circuit presenting a thin gate oxide to the I/O pad, it will be destroyed even prior to clamp triggering. The traditional solution is adequate for thick gate I/O transistors, but not for core transistors. That is why the PDK will flag and not allow core transistors in combination with standard I/O ESD protection solutions.
A specialty SCR-based solution may work – and does work as demonstrated in our article about Diode triggered SCR ESD protection clamps (Link). The most important thing now is to engineer your solution such that it acts fast enough, for example, under CDM stress conditions with sub nano-second rise times.
Sofics is a specialized ESD solutions developer who licenses solutions silicon proven (across a wide range of advanced technologies and foundries) for this particular problem.
Thin gate transistor interfaces are especially desired for in-package die-to-die interfaces, for very high-speed applications and low noise designs (Link).
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