Selecting custom ESD IP for your next IC

Fabless semiconductor companies usually use third-party IP blocks when developing ICs. An important IP is on-chip ESD protection. Caution must be exercised in choosing the right ESD IP to avoid patent infringement and inefficient ESD clamps.

ESD IP of choice should be silicon proven and directly compatible with your usual design process. Thomas Ako made a presentation about the IP selection process on the 2021 IP-SOC event in Grenoble in December 2021.

Introduction

When selecting Semiconductor IP blocks for a new ASIC there are 3 main sources.

Foundry: Most foundries provide (foundation) IP like standard libraries, memory, I/Os. These IP blocks are provided free-of-charge, included in the wafer price
Third party IP: Every foundry has built up an IP ecosystem of proven IP blocks from trusted companies. An ‘ 1/n’ business model is used. IP companies pre-develop circuits that can be used by many. The development cost is shared across ‘n’ companies. IC designers pay NRE and or royalties
Fabless in-house teams: Every fabless company also builds IP blocks and circuits for their own needs. This is the most expensive IP because the re-use opportunity is smaller

For On-chip ESD protection clamps there are also 3 sources. ESD clamps are required to protect sensitive circuits and to ensure high yield during production and assembly.

Foundries typically provide GPIO libraries that include ESD protection cells.
ESD can also be licensed from companies like Sofics (License)
In-house ESD teams sometimes develop their own ESD cells (Make)

When the foundry solution is not good enough fabless IC designers have to decide: either create the ESD cells in-house or license IP from Sofics.

Case study: Extending the foundry I/O libraries

Foundries provide GPIO libraries with integrated ESD protection. The general purpose library can be used by many IC designers and across verticals.

However these libraries have a number of limitations.

The I/O voltage range is limited
The conventional ESD approach introduces a lot of leakage
The ESD robustness is limited to 2kV HBM
The standard analog I/Os have a lot of parasitic capacitance
The total ESD area can be quite large.

Sofics has developed ESD clamps that can overcome these limitations.

Sofics background

Over the last 20 years, Sofics has supported more than 100 fabless companies. Our engineers have developed solutions that can be used for any CMOS, FinFET, SOI or BCD platform. There are 3 main reasons why customers work with Sofics.