Local ESD protection in analog IOs

In the connected world today, the demand to transfer data is growing every day. People increasingly consume streaming video content, at home and on the road. The increased bandwidth is needed on every level, from smartphones, PCs, at data centers and across long distance connections. This demand pushes the semiconductor industry to develop faster communication solutions for wireless, optical and wired interfaces.

For such high-speed communication interfaces chip designers need to limit the parasitic capacitance of the on-chip ESD protection clamps connected to the interfaces.

Traditional ESD approach for analog I/Os

The traditional ESD approach for analog I/O pads is shown below in Figure 1. It consists of a diode from Vss to the I/O pad, a second diode from I/O pad to Vdd and a power/rail clamp between Vdd and Vss. IC designers like it because the 2 diodes are easy to implement, have a small silicon footprint and have reasonably low parasitic capacitance.

Figure 1: The traditional ESD approach for many I/O pads: A diode from Vss to I/O and another diode from I/O to Vdd. A power clamp is required for half of the stress combinations.

For sensitive nodes, IC designers add an isolation resistance from I/O to the circuit to increase the ESD design window. If the functional circuit cannot handle any ESD current, a secondary clamp is added behind the isolation resistance: Figure 2.

Figure 2: Sometimes IC designers add a resistance between I/O pad and the circuit and implement a small secondary clamp just before the sensitive circuit. This can increase the ESD design window.

There are several issues with these simple ESD approaches, specifically for high speed interfaces:

  1. The isolation resistance severely impacts behaviour at high speeds and adds noise.
  2. The ESD diodes may introduce excessive parasitic capacitance between the signal pad and the power lines.
  3. Some interfaces cannot tolerate a diode from I/O pad to Vdd due to matching, due to noise coupling between pad and Vdd or because the signal voltage can be higher than the reference Vdd voltage.
  4. For sensitive nodes the total voltage drop over the intended ESD current path can be above the failure voltage of the functional circuit.

A simple way to reduce the capacitance (issue 2) and increase the voltage tolerance (issue 3) is to use 2 or more diodes in series. However, this leads to a higher voltage drop during ESD stress, deteriorating issue 4. An alternative with a novel dual bipolar concept [Link] was presented in 2017.

Local clamp ESD approach for analog I/Os

This article discusses an approach where IC designers replace the traditional dual diode ESD concept with a local protection clamp concept, simplified in Figure 3. If the functional operation cannot tolerate a diode from ‘IN’ to Vdd that diode can be removed. That is typical for fail-safe, Hot-swap, open-drain outputs, cold-spare inputs or overvoltage tolerant interfaces.

Figure 3: Simplified circuit schematic with a local clamp ESD protection approach. The diode between IN and Vdd can be removed if needed for the functional operation. In some cases, another clamp is added between Vdd and ‘IN’.

The local clamp approach introduces a lot of benefits:

  1. Reduced dependence on bus resistance
  2. Strongly reduced voltage drop under ESD conditions without the need for an isolation resistance, perfect for sensitive nodes.
  3. Different options to reduce the parasitic capacitance
  4. Can be optimized for each I/O pad separately. E.g. some pads may need higher ESD robustness or cannot tolerate a diode between I/O and Vdd.

More information?

Dual-diode based ESD protection is used a lot. However, some interfaces need another type of protection. A local ESD clamp in the IO area has many benefits. Sofics engineers have supported more than 100 fabless companies with customized local clamp solutions.

  • Especially high-speed communication requires local clamps with low parasitic capacitance. You can get more technical details in peer-reviewed papers (2019, 2017, 2012) on our website.
  • Some interfaces need higher voltage tolerance. In that case a diode to Vdd can be problematic. A local clamp concept can solve that. More information in our 2011 paper. [Link]
  • Several applications (automotive, medical, consumer, HDMI, DisplayPort, USB, …) require much higher ESD robustness. Typically, most IOs are protected up to the standard 2kV HBM level. But interfaces that connect outside of the system need higher robustness. In 2009 an example solution for HDMI was presented [Link].
  • Contact us if you like to discuss your application.

Published by 32bartkeppens

Sofics provides solutions for the ESD/EOS/EMC robustness of integrated circuits. We have a 20+ years track record, supporting 100+ fabless companies worldwide with on-chip ESD protection and custom/specialty Analog I/O’s and PHY’s. Solutions in CMOS, BCD, FDSOI and FinFET technology are available off-the-shelf Since 2019: Sofics: Responsible for business Development worldwide 2009 - 2019: Sofics: Technical marketing director 2006 - 2009: Sarnoff Europe: Support for business development 2002 - 2006: Sarnoff Europe: Solving ESD related issues for customers worldwide 1996 - 2002: Imec, Belgium: Member technical staff Topics: on-chip ESD protection, ESD analysis, non-volatile memories 1996: Engineering degree in electronics from Groep T, Leuven, Belgium (co-) authored more than 40 peer-reviewed published articles.

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