3 approaches to handle EOS ‘requirements’

EOS, or Electrical Overstress, is an electrical stress that exceeds any of the specified absolute maximum ratings (AMR) of a product. Sources claim that more than 40% of the field failures in electronic products are related to EOS.


An example is when an IC customer applies the wrong voltage to chip interfaces. For example, a 3.3 V I/O is designed for voltages up to 3.63V. In most cases accidently applying 12V on those pads will lead to failure of the circuit. When a circuit is connected to a battery with the wrong polarity it could also cause a problem.

From “Rethinking Electrical Overstress” – link

But it is not only due to wrong handling by people. One of the cases is related to lightning events during a thunder storm. Such a strike cannot be handled by typical CMOS integrated circuits because the current and voltage are excessive. However, when a lightning event strikes a house all appliances (TV, radio, computer, fridge, microwave, …) will see a residual current/voltage stress. Similarly, but at much lower amplitude, is overstress generated by switching events.

By definition you cannot protect against EOS because then it is no longer called overstress. One can try to extend the absolute maximum ratings to cover more cases. For the 3.3V interface example, the IC designer could change the interface circuit and its ESD protection clamp to tolerate voltage of more than 12V. This will extend the absolute maximum rating. Such a design change is not easy. Chip designers will only consider such a change if it is really necessary.

Three main challenges

There are 3 challenges

  • Identify the conditions in the field leading to failures.
  • Find a way to reproduce the failures in the lab to study the problem and solutions
  • Extend the absolute maximum rating to prevent such failures in future designs

This article focusses on the last challenge.

Example: high voltage tolerance

Generic semiconductor products that are used in different applications could prevent EOS issues by designing the chip interfaces with a high voltage tolerance and flexible voltage levels for operation. For instance, many of the FPGA standard I/Os can operate on a wide voltage range like 1.2V to 3.3V. Analog products for DC/DC conversion for generating 1.8V have a flexible input signal ranging from 2V to 10V for example.

In under-the-hood systems in automotive applications IC designers frequently include “battery reversal” protection.

Case study: IEC 61000-4-5 requirement

IEC 61000-4-5 is one of the many standards published by the international electro technical committees (IEC) relating to the electromagnetic compatibility (EMC) of systems. This specific standard relates to the immunity requirements caused by over voltages from switching and lightning transients.

The simulator has an internal 2 Ohm resistor. This means that 100V at an open circuit correlates to 50A for a short circuit. Systems, stressed at the power supply, can achieve a level between 0.5 kV to 4kV. At this level the current (250A to 2000A) is too high to sink safely through CMOS on-chip protection circuits. This IEC61000-4-5 test is not really designed to validate separate IC devices. The resulting current is too high.

Short-circuit current waveform (8/20 us) at the output of the simulator

More than a decade ago, a big consumer brand selling flat panel TV sets received several field returns. Their analysis on the returned TVs showed damages in the timing controller chip (TCON). The timing controller chip is the interface between external signals received by the TV set and the internal display driver chips. In their analysis, they could replicate the failures by applying high current/voltage pulses on the interfaces following the IEC 61000-4-5 standard (link).

Since then, this system manufacturer started enhancing the requirements for their timing controller suppliers. Now, besides HBM ESD requirements, the 3.3V interfaces must be able to sustain up to 12V stress. Clearly the design of the I/O circuit and the ESD clamp is completely different to survive that kind of stress. Below are 3 different approaches to handle that requirement.

Approach 1: increase voltage tolerance

In the first approach the IC designer changes both the I/O circuit and ESD protection clamps. To increase the voltage tolerance of input/output drivers one can connect multiple devices in series to divide the voltage across them. This is not so easy. It involves adding bias voltages for intermediate nodes to ensure the voltage drop across every junction/gate remains within the limits.

Another option is to rely on transistors with intrinsic higher voltage tolerance. Some foundry processes have (optional) high voltage devices like NLDMOS transistors. Due to lower doped junctions the breakdown voltage is higher.

Also for the ESD protection clamps different solutions exist. Output drivers are frequently made ‘self-protective’ but that is not straightforward for the cascoded designs nor for the NLDMOS high voltage transistors. Unfortunately these transistors are rather weak during ESD stress (link).

At Sofics we have designed unique ESD clamps that are placed in parallel with the I/O tolerant circuits. One of our customers asked for an ESD protection for their 12V interface on TSMC 28nm CMOS technology. The clamp triggers at 13.7V and has a holding voltage of more than 13V.

ESD protection clamp verified on TSMC 28nm – 1.8V process. With a trigger and clamping voltage beyond 13V it can be used for e.g. 12V interfaces.

Approach 2: secondary protection approach

In another approach to protect against IEC 61000-4-5, IC designers keep the I/O circuits the same. The 3.3V interface in the example is created using regular 3.3v transistors. Only the ESD protection clamps are changed.

The ESD protection consists of 3 elements

  • Primary ESD protection with high voltage (e.g. 12V) tolerance
  • Isolation resistance
  • Secondary ESD protection close to the I/O transistors.

The primary ESD protection must be able to tolerate the high voltage. Ideally trigger and clamping voltage are higher than the DC stress voltage. The clamp shown above could be used here too.

The secondary protection is similar to the regular ESD protection for 3.3V interfaces. It can be based on self-protective output drivers or a parallel ESD protection clamp. For example, a local ESD clamp for the 3.3V interface triggers at 4.5V and has a holding voltage of 4V. This will ensure the interface is protected during ESD stress events.

However, the ESD path must also be able to handle stress current during long duration (DC-like compared to ESD) stress. If 12V is applied at the bond pad, current will flow through the isolation resistance and through the secondary protection clamp. Obviously, the amount of current through the secondary path will be bigger if the isolation resistance is smaller and the clamping voltage of the ESD cell is lower. The aim is most of the voltage is across the resistance. For a holding voltage of 4V (secondary protection) this means 8V is across the resistance. If the IC designer can include 100 Ohm isolation resistance the current is less than 100mA.

Approach 3: use resistance in the test system

The test system used for the IEC61000-4-5 tests has a 2 ohm output resistance. In the 3rd approach one could rely on this resistance in a similar way as the secondary protection described in approach 2.

This means IC designers use the standard interface circuits and ESD devices for each of the interfaces but with higher current capability. For example the ESD protection for the 3.3V interface has a clamping voltage of 4V. The test system however applies 12V across the 2 Ohm output resistance in series with this ESD clamp.

This means there should be 8V across the 2 Ohm resistance, which leads to a current of 4 Ampere. All the connections (metal traces) and ESD devices must be able to handle this amount of current.

Because the time duration for the IEC61000-4-5 stress is much longer than a typical ESD event IC designers should use the right failure information. At Sofics we therefor measured the failure current for metal traces and ESD devices under different pulse widths from ESD time domain to several us.

Example data for GGSCR ESD clamps and metal traces under pulsed stress with different pulse durations. The failure current at long pulses (50 us) is much lower compared to the failure current during ESD relevant periods (~100ns).

The longer the pulse duration, the lower the failure current. Clearly the devices and metal traces need to be a lot bigger for 4A under 50us compared to 4A under 100ns ESD stress.


Extending the absolute maximum rating for IC interfaces is not easy. It will require updates in the I/O circuits, ESD devices and metal connections. The best approach depends on the process technology, ability to include resistance and application considerations.

Sofics has provided high voltage tolerance ESD clamps for several cases.

  • Timing controller products for flat panel displays
  • Set-top-box devices with high-speed DisplayPort and HDMI interfaces
  • Automotive applications
  • Industrial communication

Contact us to discuss your IC design constraints.

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Published by Bart Keppens

Chief Business Development at www.sofics.com Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog IOs and on-chip ESD protection. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. Our technology has been characterized on 11 foundries including advanced nodes at TSMC, UMC, GF, Samsung Foundry.

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