ESD protection for Internet-of-Things (IoT)

What is the right ESD requirement for IoT applications? The internet of Things circuits are used in new environments. It is not possible to use the same reliability approaches for all the different applications. Sofics’ CEO Koen Verhaege presented an overview on the 2018 IoT workshop.

This presentation helps the audience to select the right ESD/EOS/latch-up requirements for IoT applications. Many Internet of Things (IoT) applications can be made in older, depreciated fabrication plants (0.25um, 180nm, 130nm) that were top-notch 10+ years ago. We learned, by supporting innovative semiconductor startups, that many of the applications in IoT require special attention with respect to ESD and EOS protection.

The slides can be browsed below.

Problem statement

Sofics ESD-IP has been integrated into thousands of IC designs in the last 20 years. We have supported many different applications. Initially our customers asked for 2kV HBM, 200V MM and 1kV CDM but over the years these requirements have changed a lot. In the past the weakest pin combination defines the ESD robustness of an IC.

Today there is much more variations of ESD robustness for the different stress combinations. Some pins need (much) higher ESD robustness. Some combinations on the other hand can tolerate lower levels. ESD qualification used to be performed on un-powered devices but that also changed. Customers also came up with creative experiments to stress devices.

Challenges for IoT devices

Internet of Things is a network of physical devices, embedded with electronics. There are several challenges from privacy, wireless connectivity, integration, cost reduction. For ESD engineers the key aspects to worry about are ensuring high performace is possible without excessive leakage/power. In several applications the ESD robustness must also be increased.

Risk analysis

In IoT applications electronic circuits are integrated into all kinds of devices. This means that chips end up in new environments and new use cases. Therefore it is important to perform a risk analysis for every new application.

The risk analysis includes identification of the threats, assessing vulnerability, determining the likelihood of ESD stress and assessing the impact of a possible ESD failure. IC designers could use the ISO 31000 approach.

Case studies

The presentation covers 7 different IoT applications and provides a risk analysis for each example to derive the ESD/EOS requirements. Applications covered include indoor positioning, NFC, medical, implanted devices, wearables, smart home and industry 4.0.

The examples show that each application is different. A generic ESD protection level across markets cannot be established. Sometimes a much higher robustness is required and specialized reliability tests are used.

  • Case 1: IoT at the cloud side (link to article about silicon photonics)
  • Case 2: Industrial, indoor positioning (link to article about LNA protection)
  • Case 3: Near Field Communication (link to article about clipping circuit)
  • Case 4; Body implanted devices (link to article about medical devices)
  • Case 5: Wearable devices (link to article about overvoltage tolerant ESD)
  • Case 6: Smart home (link to article about system level ESD protection)
  • Case 7: Industry 4.0

Summary and conclusion

Clearly, the ESD robustness requirements depend on the application. Component level ESD used to be about ensuring the IC is protected during manufacturing, assembly and testing. In IoT applications some interfaces will need higher ESD robustness to ensure the circuit is not damaged from ESD stress during the functional operation of the system.

Contact us if you like to discuss your own IC project.

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Published by Bart Keppens

Chief Business Development at www.sofics.com Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog IOs and on-chip ESD protection. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. Our technology has been characterized on 11 foundries including advanced nodes at TSMC, UMC, GF, Samsung Foundry.

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