ESD protection for 8.5 GHz LNA in 90nm

Nowadays, mobile consumer electronics devices integrate wireless interfaces like WIFI, Bluetooth, GPRS and GPS. Various approaches exist to protect the wireless interfaces against ESD stress. In the recent decade, researchers have focused on so-called ‘co-design’ techniques to solve both functional and protection constraints together which requires both RF and ESD design skills.

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However many IC designers still prefer to work with ‘plug-n-play’ protection concepts where the ESD clamps exhibit low parasitic capacitance, low series resistance and low leakage. This article shows measurement results of an SCR based protection approach that exhibit low and stable parasitic capacitance over a broad voltage and frequency range. The clamp is used for protection of an LNA circuit in 90nm CMOS technology.


Despite the improved ESD awareness and control in assembly factories and the related push for a reduction of component level ESD performance IC’s still need adequate ESD protection. In many cases, traditional ESD protection devices used for low speed digital interfaces offered by foundries, IO library providers are not suited for the RF interfaces for a number of reasons:

  • Capacitive loading shunts large part of the RF signal to Vdd/Vss lines due to high parasitic junction and metal capacitance of ESD clamps.
  • Increased noise injected at the receiver due to series resistance used between primary and secondary ESD clamps
  • DC leakage current degrades Q-factor and influences the size of the bias circuits

To reduce the cost of consumer electronics devices designers also try to combine different standards into a single silicon die adding more constraints for the ESD protection approaches: the clamp parasitic influence should be as stable as possible across a large frequency band and voltage range.

ESD protection for wireless interfaces

IC designers use a variety of ESD protection approaches to protect integrated circuits against ESD stress. The well known ‘dual diode’ based ESD protection has been used by many designers for the protection of analog circuits thanks to the small area, straightforward implementation, low leakage and low capacitive loading. Recently however various researches have predicted the end of ‘dual diode based ESD design’ for RF circuits in advanced CMOS (65nm and beyond) due to the shrinking ESD design window of the sensitive circuits. They explain that to ensure effective protection the diodes connected to the IO’s must be designed with larger perimeter to reduce the voltage drop (Ron x IESD) which in turn leads to higher leakage and higher capacitive loading worsening the RF performance of the connected circuits.

Fortunately there are alternatives to protect RF circuits against ESD stress.

  • Plug-n-play, minimal parasitic capacitive loading: The parasitic capacitance of the ESD devices is minimized such that the degradation of the RF performance is limited. Researchers have compared different device types for this purpose.
  • ‘LC’ Cancellation techniques: In various publications designers compensated the parasitic effects of ESD devices by adding tuned LC elements
  • Co-design: Through the use of ‘co-design’ traditional ESD solutions with high capacitive loading can still be used because the negative effects are compensated for in the matching circuits.

Below is a case study based on one specific protection approach: plug-n-play protection with low capacitive SCR based protection. The example is about the IEEE 802.15.4a standard used for Real Time Location Systems (RTLS) but the ESD devices can be used more broadly thanks to the low parasitic capacitance, high Q factor and low leakage.

ESD protection for 90nm LNA

An SCR based protection clamp is validated for an 8.5 GHz LNA designed in TSMC 90nm LP. The ESD protection is designed to protect the ultra-wideband RF circuits based on the IEEE 802.15.4a standard. 802.15.4a is an alternate PHY and adds location awareness, low power and higher data rates to the PHY and MAC specification for Zigbee devices. The circuit can be used for accurate real-time indoor location of resources/assets and in wireless sensors for health, retail, manufacturing and security sectors. One of the key requirements is the low leakage core and IO circuits: The chip operates off a single watch battery for up to 10 years.

The proprietary circuit to be protected consists of 3.3V transistors leading to a failure voltage (ESD design window) of 11.4V enabling various ESD protection concepts. To leave room for a large analog circuit including coils on the top metal, the IO ring is designed such that there is only a low resistive Vss bus available at the RF interfaces which means that a ‘dual diode’ protection approach is not feasible. To enable the high frequency signals the parasitic junction capacitance of ESD clamps has to be below 100fF. Furthermore the clamp leakage at room temperature must be below 1nA.

The selected protection design consists of an SCR clamp triggered by a NMOS device with dynamic gate bias as shown in figure below.

Schematic of the MOS triggered SCR protection clamp.

The layout includes the SCR clamp, NMOS trigger, RC ESD detection filter, reverse diode and all required guard bands within an area of 55.91um by 52.08um. Thanks to this small area the ESD cell could be located under the bond pad (Circuit under Pad – CUP) leaving room for the large area inductors of the RF circuit.

Layout view of the MOS triggered SCR protection clamp. The total silicon footprint is less than 3000um² and could easily fit under the bond pad.

Besides the IO pad and a low resistive metal connection to Vss, a narrow connection to Vdd is required to keep the capacitance of the RC detection circuit charged up during functional operation of the circuit and to keep the diode from pad to anode reverse biased.

The parasitic capacitance loading of the ESD clamp is calculated based on available models from the foundry following the equivalent circuit consisting of 9 junction capacitances and 7 metal capacitance values. Total IO capacitance is less than 100fF.

Equivalent circuit for the calculation of parasitic junction and metal capacitance. Total capacitance at the IO’s is 98.62fF

The ESD design guarantees effective ESD protection up to 2kV HBM, well above the standard requirement used for RF interfaces in advanced CMOS technology. This means that the chip can be handled in low cost assembly houses to push down the cost of the system.

Thanks to the low capacitive loading of 98.62fF and low leakage below 0.1 nA (@ 25°C), 55nA (@ 125°C) the clamp does not influence the RF behavior thereby greatly simplifying the design of the RF circuits.


This article provided information about an SCR based ESD protection clamp for RF circuits validated in TSMC 90nm CMOS technology. The ESD protection clamp described has excellent figures of merit: Due to the low parasitic capacitance, low leakage and high Q-factor the influence on the RF performance is limited. RF designers can rely on SCR clamps without the need for extensive co-design optimizations between RF (matching) circuitry and ESD protection devices.

While this paper focused on the IEEE 802.15.4a standard the ESD device concepts can be used more broadly for both high frequency RF IO’s as well as high speed differential, digital interfaces like HDMI and USB 3.0.

Want to read about additional examples of ESD protection for LNA circuits: link.

Contact us know if you like to discuss ESD protection of your wireless interface.

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Published by Bart Keppens

Chief Business Development at Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog IOs and on-chip ESD protection. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. Our technology has been characterized on 11 foundries including advanced nodes at TSMC, UMC, GF, Samsung Foundry.

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