On-chip ESD protection devices are used to prevent damage during Electrostatic Discharge (ESD) stress from wafer production till the assembly of the chips on the PCB in the application. For instance, ESD stress events can occur during the process of connecting the die interfaces (bond-pads) to the package pins. Fortunately these ESD threats can be controlled with factory ESD control measures like ionizers, grounding of machines and personnel. Thanks to better understanding and improved control measures, the typical 2kV component level HBM requirement that was used in the industry for many years has been reduced to 1kV or lower.
This article discusses ESD stress events on the system level, when the system is used. While it is easy to control the potential of machines and people in the semiconductor manufacturing and assembly processes that is not so easy for finalized systems (smartphones, cars, PCs, laptops, TVs). Clearly ESD events can occur when systems are used in the field. This stress can create failures on the boards and in the packaged chips.
During ESD stress the protection devices on the chip create a current path to ground. The total voltage drop of this shunt path should be as low as possible to protect the functional circuitry (link: more info about the ESD design window article). For instance, a power clamp from Vdd to Vss needs to limit the voltage difference between the supply lines below the failure voltage of the core circuit. Very large chips (like a CPU chip) could rely on the (decoupling or parasitic) capacitance between the two supply lines for ESD protection. If the total capacitance is big enough (e.g. compared to the HBM capacitor) a rail clamp is not required because the voltage difference will stay low anyway.
The on-chip protection devices are verified using component level tests like Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). The behavior is analyzed with TLP testers (link).
System level ESD
Once the IC is integrated on a Printed Circuit Board (PCB), the on-chip ESD protection elements are not activated that frequently anymore. That does not mean that there are no ESD events. But once the chip is integrated on the PCB it is also protected by the PCB and additional discrete components.
- PCB designers add large decoupling capacitors between the Vdd and Vss lines to stabilize the voltage of the power lines. These board-level capacitors prevent a sudden voltage difference between the Vdd/Vss pads.
- PCB designers also integrate board-level protection and filter elements to protect I/O lines. Transient Voltage Suppressors (TVS) protect the circuits against stress on the system level.
- Further, the resistance and inductance of the PCB traces also help to reduce ESD stress on the chips.
- Sometimes capacitors are added on the signal lines
- Guard traces on the PCB prevent indirect ESD hits to signal traces
- Typically the signal pins that connect to the outside of the system are shielded. The well-known USB connector for instance is designed such that an ESD zap will most likely reach the grounded shield rather than one of the signal pins.
The most used test to replicate ESD events for systems is the IEC 61000-4-2 test. The IEC 61000-4-2 requirement is defined for testing complete systems (car, TV, smartphone). However, nowadays the system tests are also applied directly on sub-boards or packaged chips. It could be relevant for interface pins where the distance between the connector on the system and the chip is kept short for improved signal integrity. In some cases (e.g. IoT devices, smartphones) there is not enough room on the PCB to add board-level ESD protection.
It is important to understand that an 8kV IEC 61000-4-2 contact discharge test involves a high peak current, much more than an 8kV component level HBM stress.
At Sofics, we strive to develop the best on-chip ESD protection solutions, extending the library offered by foundries. Our customers set the ESD requirements (mainly HBM and CDM) that the custom solutions need to pass. In the last 10 years we frequently got requests to provide on-chip ESD protection solutions that can also pass 8kV contact discharge according to IEC 61000-4-2. You could think of it as an on-chip TVS (transient voltage suppressor – link).
Unfortunately, the IEC61000-4-2 test conditions are not defined for such use case which means that the test approach strongly differs between companies. Some use a mock PCB, some stress the chip pins directly, others connect a (USB/HDMI) cable to the system and then cut the cable to be able to stress on the signal lines. Therefore, a request for IEC 61000-4-2 robustness on the chip always starts with a discussion about the test conditions. Somehow we need to find out which part/fraction of the stress current will reach the chip.
For on-chip TVS there are a 3 main aspects that need to be covered.
- System level ESD stress introduces a much higher ESD current than component level ESD stress. So the on-chip ESD devices must be scaled up. We have proven that our device concepts can be scaled easily to higher ESD levels on various process platforms. Because there is no standard to apply IEC 61000-4-2 stress on chips we frequently design the ESD clamps for the worst case situation that all of the ESD current flows through the on-chip ESD device. For a 8kV IEC stress level we scale the ESD clamps to 16A of TLP current or 24kV HBM. The table below shows results for scaling of Sofics proprietary Diode Triggered SCR devices in a 65nm CMOS technology.
|ESD protection level||Silicon area|
|2A TLP – 2.8kV HBM||35 um x 22 um = 770 um²|
|3.6A TLP – 5kV HBM||35 um x 38 um = 1330 um²|
|7A TLP – 10kV HBM||60 um x 40 um = 2400 um²|
|8kV IEC 61000-4-2 contact||120 um x 54 um = 6480 um²|
|12kV IEC 61000-4-2 contact||175 um x 54 um = 9450 um²|
- System level ESD stress has a very fast rising edge, from zero to peak current within 1ns. Similar to CDM stress it could lead to damaged circuits if the ESD clamps do not act/trigger fast enough. Sofics verifies its ESD clamps with a so-called Very Fast-TLP (VF-TLP) system. We apply the VF-TLP stress on bare dies/wafer through matched RF-probe needles to ensure the fast pulse transients with ~200ps rise time reach the device. The typical pulse width is ~5ns. Most ESD devices will be able to tolerate a higher current level during the shorter pulse width. However, due to the fast transients the devices may exhibit a voltage overshoot that can damage oxides or trigger an NPN into a destructive snapback. During our tests we apply the fast stress on stand-alone clamps as well as on ESD devices in parallel with victim circuits to check if the clamps are effective (example for advanced nodes – link).
- System level ESD stress is frequently applied on powered systems. If the IEC stress is conducted on-chip this may cause latch-up issues if the ESD clamp holding voltage is below the power supply voltage, or if the ESD clamp injects carriers into the substrate and triggers a parasitic device with a low clamping voltage. Sofics uses different test systems to address these kind of issues. Sofics engineers have developed ESD concepts with high holding voltage (some beyond 40V) to ensure latch-up safety can be guaranteed, even during the severe IEC 61000-4-2 ESD stress under powered conditions.
Our engineers have provided on-chip TVS for several applications like.
- 0.35um CMOS – USB interface pads – protection of the signal pins to 8kV (Contact) and 15kV (air) IEC 61000-4-2
- 180nm CMOS – IoT sensor applications – protection of the SoC against 15kV air discharge
- 130nm CMOS – HDMI switch interfaces – protection of high speed signal pins (3 Gbps) to 8kV IEC 61000-4-2
- 40nm and 28nm CMOS – DisplayPort interfaces – Protection of high speed signals (10 Gbps) to 4kV and 8kV IEC 61000-4-2
- 0.25um BCD – Automotive LIN transceiver – protection against 6kV and 8kV IEC 61000-4-2
- 180nm BCD – Automotive applications – protection against 6kV and 8kV IEC 61000-4-2
Despite the fact that IEC 61000-4-2 is a standard created for system level ESD stress it is frequently used for stand alone integrated circuits. The test approach for chips is not defined nor standardized for this requirement so it is important to have a discussion on the test conditions and acceptance criteria. This article outlined 3 aspects that need to be considered if on-chip ESD protection needs to withstand the IEC 61000-4-2 stress.
Contact us if you need help to protect your chip against system level ESD stress events.