6 concepts to replace dual diode ESD protection

The ‘Dual diode’ approach is one of the most used on-chip and off-chip concept for ESD protection of IO interfaces. It is simple to implement, smaller than any other IO/ESD concept, has a low parasitic capacitance and low leakage.

Dual diode based ESD protection concept for IOs.

However, especially the ‘diode up’, from IO-pad to VDD can create a lot of problems in the functional operation of Internet of Things (IoT) circuits. There are basically 3 main reasons why the ‘dual diode’ concept is causing trouble.

  • When the I/O signal voltage exceeds the Vdd power line voltage the ‘diode up’ is forward biased. That is not tolerated during functional operation.
  • Open-drain based communication (e.g. I2C interface) does not allow a diode from IO to Vdd
  • When sub-systems of the SoC are powered-down signals at the I/O could still power-up the Vdd line through the ‘diode up’

Fortunately, there are many different concepts that IC designers can use. Below you can find 6 different concepts that you can use to replace the dual diode protection.

Concept 1: Series connection of diodes

Sometimes the IO pad voltage can exceed the Vdd power voltage with several volts, e.g. during transients. To prevent an increase of the Vdd potential during those transient events the ‘diode up’ ESD protection must be replaced. In this concept a chain of diodes is used instead of a single diode between the IO pad and the Vdd power line. This increases the threshold for (ESD) current from PAD to Vdd. This is a simple concept within a small area. Due to the sequence of diodes the parasitic capacitance of the ESD cells is actually smaller than the single diode. The leakage can be lower too. The simple concept can be tuned by selecting the right number of diodes.

There is a main drawback to this approach. During ESD stress from PAD the voltage drop across the chain of diodes is larger than for a single diode. Functional circuits in parallel of the ESD current path may get damaged. This concept cannot be used to protect sensitive IO circuits.

Concept 2: ESD clamp to Vdd

In case that the IO pad signal voltage can exceed the Vdd voltage by a lot, the first concept is not possible. Too many diodes would be needed. Sometimes people include a separate ESD device from pad to Vdd. It is a simple concept and can be a low leakage solution.

However, also this concept has drawbacks. A dedicated ESD clamp requires more silicon area. The capacitance will typically increase too. Unlike the tunability of the first concept the trigger voltage of this concept is fixed by the clamp type. Similarly, as in for the first concept, it is possible that it introduces a high voltage drop during ESD stress.

Concept 3: Another supply reference

Some designers really want to use ‘dual diode’ based ESD protection at the IO pads. To overcome the issues, they connect the ‘diode up’ to another Vdd reference with a higher voltage on the chip. The IO-pad layout remains simple. The parasitic capacitance and leakage stay the same as the dual diode case.

This concept is really simple. However, it can only be used if there is a Vdd-2 reference supply level with high enough supply voltage. In most cases such a higher voltage reference is not available. Moreover, the metal routing is more complex. Also, Vdd-2 must be biased whenever the IO pad signals are active. The ESD stress path must be carefully looked at and compared to the ESD design window of the circuit for stress from PAD to VDD for instance.

Concept 4: ESD bus

Similarly, to the third concept, IC designers can tie the diode up to another supply bus. In this concept, however the ESD bus remains internal to the chip.

It is a simple concept but you will need an additional power clamp and extra metal routing for the ESD bus.

Concept 5: Self-protective driver

In various process technologies it is possible to create so-called self-protective NMOS drivers. In that case the ‘open drain’ driver protects itself and there is no need for an ESD path through diode up and power clamp. The parasitic bipolar NPN device hidden inside the NMOS is triggered and shunts the ESD current from PAD to ground/Vss. This concept is used a lot in mature process technologies, certainly if the output driver is designed for large currents under normal operation. Because the driver is required anyway there is no additional ESD related parasitic capacitance or leakage.

Unfortunately, this simple concept cannot be used for every over voltage tolerant or open-drain interface. Our research on advanced CMOS and FinFET technology shows that NMOS transistors are easily damaged during ESD stress. In these recent processes the parasitic bipolar device in the NMOS is damaged even at low ESD stress levels. Sometimes the process engineers also provide NMOS devices with a higher voltage tolerance. However, for these devices we noticed a lot of gradual degradation under repeated ESD stress.

Concept 6: Local clamp protection

In the last concept the IO circuit is protected by a parallel ESD clamp device. It can consist of a clamp between PAD and VSS or a pair of clamps. The designer cannot always count on self-protective drivers (concept 5) or another reference (concepts 3, 4). There are many clamp devices available. The optimal solution depends on the other requirements like leakage, capacitive loading and available area at the IO circuit.

The main drawback of this approach is the additional silicon area required for the parallel ESD device. Fortunately, several SCR based solutions can be effective even in a small area.

More information?

  • Read about the 3 cases where dual-diode based ESD protection is not feasible [Link]
  • Find out different cases where local clamp solutions provide benefits in a peer-reviewed publication at the 2019 Taiwan ESD and reliability conference. [Link]
  • Or read about solving ESD protection for hot-swap, failsafe and open-drain interfaces in a publication at the 2011 Taiwan ESD and reliability conference. [Link]
  • Contact us if you like to discuss how Sofics local clamp ESD protection approach can enable your application.

Published by 32bartkeppens

Sofics provides solutions for the ESD/EOS/EMC robustness of integrated circuits. We have a 20+ years track record, supporting 100+ fabless companies worldwide with on-chip ESD protection and custom/specialty Analog I/O’s and PHY’s. Solutions in CMOS, BCD, FDSOI and FinFET technology are available off-the-shelf Since 2019: Sofics: Responsible for business Development worldwide 2009 - 2019: Sofics: Technical marketing director 2006 - 2009: Sarnoff Europe: Support for business development 2002 - 2006: Sarnoff Europe: Solving ESD related issues for customers worldwide 1996 - 2002: Imec, Belgium: Member technical staff Topics: on-chip ESD protection, ESD analysis, non-volatile memories 1996: Engineering degree in electronics from Groep T, Leuven, Belgium (co-) authored more than 40 peer-reviewed published articles.

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