Optical communication also requires ESD protection

In the past, Fiber-optic communication was used for long distance communication (50 km and beyond). Only a limited number of these high-end interface products were required worldwide. More recently, companies running large data centers (Facebook, Google, Amazon,…) like to replace the traditional cabling between server racks. The copper-based approach is considered a bottleneck for further improvements in data transfer capacity. Optical communication can dramatically increase the bandwidth between servers, reduce complexity, power consumption and cost.

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Reducing cost and power while increasing bandwidth

Thus, the optical interconnect suppliers now need to produce a large number of their products. They separate the optical parts (laser diodes, photo detectors) from the digital controller circuits. For the electrical ICs regular (advanced) CMOS technology can be used, providing an proven path for low-cost mass-production.

In the last decade, there were several breakthroughs for the optical components. It is now possible to use conventional CMOS processing steps to create all kinds of optical components like WDM (Wavelength Division Multiplexers), detectors, waveguides. The optical elements are typically produced in a mature SOI processes like 130nm.

Hybrid 2.5D and 3D integration

Both optical and electrical elements are then combined within a single IC package using novel and advanced packing techniques like 2.5D (electronic interposer) and 3D (flip-chip) integration. The hybrid integration allows designers to select the best process option for each function. E.g. the digital functions can be integrated in high end CMOS technology with high performance and smaller size. The photonic die does not benefit from this minimum feature size and can thus be designed in a more mature SOI technology which significantly reduces the total cost.

2.5D integration of optical and electrical IC (CPU) – Fujitsu

Optical links need custom ESD clamps

The electrical IC that is used to process the signals before transmitting or after receiving is manufactured on advanced CMOS technology like 28nm or FinFET technology. The interfaces consist of high speed (25Gbps, 56Gbps or even 112Gbps) SerDes-type circuits.

Many advanced CMOS foundries provide a set of I/O and ESD protection circuits that designers can use. However, these standard, general purpose, interface blocks are not suitable for the Silicon Photonic designs.

  • To create such high-speed differential circuits, designers utilize the thin oxide transistors. However, those transistors are very sensitive and can be easily damaged during transient events like electrostatic discharge (ESD). The maximum voltage that these transistors can endure during transient events is 4V or less.
  • Despite the fact that the sensitive pads are not connected outside of the package, they could still receive ESD stress during assembly. Therefore, adequate protection clamps need to be inserted at the bond pads. On the other hand, for signal integrity, it is important to limit the capacitance between the interface pads and the supply lines. A typical analog I/O introduces 150fF of parasitic capacitance, well above what can be tolerated by the circuit.
  • The high-speed interfaces typically operate at a voltage level below the standard I/O voltage levels (1.0V compared to 1.8V, 2.5V or 3.3V)

It is clear that IC designers need custom Analog I/Os or ESD protection for these high-speed interfaces.

Proven solutions

In the last 10 years, several companies that are designing products for Silicon Photonics have contacted Sofics for support. In those projects Sofics engineers focused on protecting the high-speed interfaces (Tx, Rx) on the electrical die as well as protection of the low voltage power pads. Sofics engineers developed ESD protection with parasitic capacitance below 15fF, ten times lower than the typical low-cap ESD protection devices in 28nm CMOS. 

More information?

Published by 32bartkeppens

Sofics provides solutions for the ESD/EOS/EMC robustness of integrated circuits. We have a 20+ years track record, supporting 100+ fabless companies worldwide with on-chip ESD protection and custom/specialty Analog I/O’s and PHY’s. Solutions in CMOS, BCD, FDSOI and FinFET technology are available off-the-shelf Since 2019: Sofics: Responsible for business Development worldwide 2009 - 2019: Sofics: Technical marketing director 2006 - 2009: Sarnoff Europe: Support for business development 2002 - 2006: Sarnoff Europe: Solving ESD related issues for customers worldwide 1996 - 2002: Imec, Belgium: Member technical staff Topics: on-chip ESD protection, ESD analysis, non-volatile memories 1996: Engineering degree in electronics from Groep T, Leuven, Belgium (co-) authored more than 40 peer-reviewed published articles.

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