Challenges for IC design in medical applications

Many medical/healthcare applications rely on semiconductor chips, certainly for the mobile and connected devices. Silicon chips enable a fast evolution and widespread use of new applications. However, integrated circuits (IC) used in medical applications require special attention for Electrostatic Discharge (ESD) protection.

Because semiconductor devices are used in new types of applications the designers must analyze the application to consider the risks.

Risk analysis

People developing new medical devices must perform a so-called risk analysis (ISO 31000). After the identification of the possible threats (like ESD events) and the vulnerability assessment the risk is analyzed. Such an analysis is a combination of 2 aspects.

  • What is the likelihood of ESD stress?
  • What is the impact of a failure due to ESD stress?

The likelihood ranges from extremely unlikely to frequent. The impact runs from negligible to catastrophic. A matrix of risks is defined by the combination as shown in the figure below.

Risk matrix – ISO 31000

If the resulting risk is low there is no need for special attention. However, for several healthcare applications the impact of a failure could be considered critical. For instance, some of the applications require ICs implanted into the body like cochlear hearing solutions. A failed chip cannot be replaced easily in such case. For a pace maker, a chip failure could even have a catastrophic impact.

Moreover, the likelihood of ESD and EOS stress is also higher in various medical applications. The chips are introduced in new harsh environments.

Special requirements

Besides the higher likelihood and possible high impact, a third aspect also requires attention. In several medical applications the IC designers cannot rely on conventional ESD protection concepts for a number of reasons:

  1. Implanted devices need a focus on low power consumption. High leakage current from the free, general purpose I/O libraries can easily neutralize the tedious work in reducing power consumption in the core circuit.
  2. IC designers need to interface at voltage beyond or below the I/O library limits. Actuators in cochlear implants, for instance, use a higher voltage, much higher than 3.3V. Some sensors run at 1.0V or lower.
  3. Several applications use wireless communication. The interface pads connected to the antenna require analog I/Os with low-parasitic capacitance.

Case study: implanted hearing aid

This application consists of 2 devices. A first part is typically worn behind the ear and includes a microphone and an audio/sound processor and a transmitter. Another device is implanted. This device has several electrodes that connect to the auditory nerves. These electrodes require a high voltage. The hearing aid uses a wireless connection for both audio signal and power transfer from the external to the internal device. The internal device does not use a battery. Designers have to employ low-power design techniques.

The risk assessment showed up as ‘moderate’. The likelihood of ESD stress is remote but the impact is critical. The ESD robustness target was set at 6kV HBM, 3 times the typical 2kV level.

A custom low-leakage ESD solution was used for the high-voltage electrodes and other pads.

Other health applications

The implanted hearing aid is just one example. There are many other types of devices. Wearable, external devices have a higher likelihood for ESD events. Life supporting supporting devices (e.g. pace maker) have a bigger impact if things go wrong.

Case study: wearable fitness tracker

Photo by Ketut Subiyanto on Pexels.com

Some consider a fitness tracker/smartband/smartwatch a health application. It allows to monitor heart rate and physical excercise 24/7. Because it is a wearable device used in daily life the likelihood of ESD events (friction between the plastic device with clothes) is rather high. On the other hand the impact is minor. The risk is tolerable. The ESD robustness level for the chips inside the smartband was set to the standard 2kV HBM level. The chips however required customized ESD clamps for a number of interfaces.

  • The core device was built using 55nm CMOS technology.
  • Several of the interfaces were built using the sensitive thin oxide transistors.
  • The wireless (Bluetooth) interface required an analog I/O cell with parasitic capacitance below 150fF.
  • The USB charging option needs a 5V tolerant interface.
  • To ensure long battery life the leakage from the ESD protection clamps had to be as low as possible.

Solutions from Sofics

Sofics engineers have supported several IC development projects for medical applications in the past.

Sofics Analog I/O and ESD protection solutions have orders of magnitude lower leakage, low parasitic capacitance and can enable interfaces at any voltage level. The ESD clamps can be easily adapted to any ESD robustness level.

Questions about your own (health) application?

Contact us if you like to discuss the risk analysis of your medical application. We can help ensure it is well protected against ESD stress.


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Published by 32bartkeppens

Sofics provides solutions for the ESD/EOS/EMC robustness of integrated circuits. We have a 20+ years track record, supporting 100+ fabless companies worldwide with on-chip ESD protection and custom/specialty Analog I/O’s and PHY’s. Solutions in CMOS, BCD, FDSOI and FinFET technology are available off-the-shelf Since 2019: Sofics: Responsible for business Development worldwide 2009 - 2019: Sofics: Technical marketing director 2006 - 2009: Sarnoff Europe: Support for business development 2002 - 2006: Sarnoff Europe: Solving ESD related issues for customers worldwide 1996 - 2002: Imec, Belgium: Member technical staff Topics: on-chip ESD protection, ESD analysis, non-volatile memories 1996: Engineering degree in electronics from Groep T, Leuven, Belgium (co-) authored more than 40 peer-reviewed published articles.

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