We often get the question: what is the CDM robustness of your ESD protection circuit? Though the question is clear, it is very hard to formulate a meaningful answer. CDM qualifies the performance of an IC or die in a specific package. Nevertheless, one expects an answer for the ESD circuit expressed in Volts.
The CDM (test pre-charge) voltage is a function of the IC’s capacitance to ground. Furthermore, the CDM discharge current flows through multiple paths through the IC all the way to the discharge pin… as a result failure may occur in the IC while the protection circuit survives the stress unscathed.
CDM voltage correlation to VFTLP current
The practical approach to provide a meaningful answer is to use the correlation between CDM (test pre-charge) voltage and the CDM (test measured) peak current as a function of a defined package. Figure 1 from the ESD Association show this correlation for BGA packages with different package sizes (which correlates with capacitance to ground).
ESD protection devices can be characterized with VFTLP: very-fast transmission line pulsing, i.e., high current (e.g., 10A) fast rise time (e.g., 200ps) short duration (e.g., 5ns) pulses. It is accepted that VFTLP measures the CDM-like stress handling capability of an ESD protection circuit.
Using Figure 1 we can answer the CDM robustness question. For example: if an ESD device can absorb 10A VFTLP within the ESD design window, we can state that this corresponds to a CDM performance of 500V in a 1500 mm2 BGA package. ESD protection devices can be designed for a specific VFTLP performance level, hence we do have a handle on its CDM robustness capability.
CDM performance of SCR devices
SCR’s (silicon-controlled rectifiers) have a reputation of being not fast enough for CDM. Many designs have failed indeed, but at the same time, properly engineered SCRs are perfect for CDM protection. The bad reputation is unfounded.
SCR’s are in essence a PNP and an NPN transistor integrated into a single device design – Figure 2 shows a schematic representation. In the equivalent circuit one sees different nodes (indicated by the yellow starred boxes), which, depending on the implementation can be assessed, controlled or driven in function of fast(er) handling ESD stress. There are different ways to implement an ESD protection based on the SCR circuit. An example of such an efficient application is the Diode Triggered SCR described in two other blog articles (Link1, Link2).
Example: comparing good and bad SCR designs
We would like to demonstrate the effect through VFTLP applied to SCR based solutions implemented in an advanced 22nm FDSOI technology – see Figure 3. The solid lines (blue, green) in the left-side plot show the VFTLP IV curves. It appears that the I-V response is good and as expected. Both designs show a solid classic-VFTLP performance, exceeding 4A.
However, as discussed in a conference paper (link) it is important to look at the transient voltage and current waveforms that are measured during the VFTLP stress. To build up a VFTLP or TLP IV-curve the system averages the waveforms at the end of the pulses as shown in Figure 4 (bottom). However, the V(t) and I(t) waveforms provide more details about the actual transient response if we look at the start of the pulse waveforms.
Every ESD clamp circuit has a certain turn-on time. During the turn-on time the ESD clamp switches from a high impedance state to a low impedance state. Especially for fast transients like CDM it is important to select ESD solutions with a short turn-on time as this will limit the voltage overshoot.
The dashed lines on Figure 3 are another type of IV curve. In those curves we plot the peak voltage data points (from the voltage transient information) against the average current value. We see a shifted curve (compared to the solid lines), an indication of the trigger speed. Or differently put: the voltage overshoot due to slow turn-on time.
The green device shows a rather large shift to higher voltages – in fact too high to effectively protect a gate under CDM stress. The green curve/device reconfirms the reputation of bad SCR designs. However, clearly, the blue curve demonstrates that SCR’s can be made fast enough, also in 22nm FDSOI. The bad reputation is unwarranted.
This approach – of plotting the so-called VFTLP overshoot curve is a quick and easy test of the trigger speed. It allows at least a relative comparison of different solution designs. It is clear that the green device is slower and will not be able to protect thin oxide transistors during CDM events.
Another way to assess the trigger speed was first demonstrated in our 2001 conference paper about GG-SCR devices (Link). In this approach the ESD device is combined with so-called gate-monitors (or other victim circuits) on the test chip to find out if the device is fast enough to protect the sensitive functional circuit.
Sofics
Sofics is a specialized ESD solutions developer who licenses solutions silicon proven (across a wide range of advanced technologies and foundries) for this particular problem.
Properly engineered SCR based solutions are especially helpful to create area efficient and ultra-low capacitance ESD protection circuits. Their application is much desired and found in high-speed, high-frequency applications.
Contact us if you like to discuss the CDM robustness of your next chip project.
Next articles…
Follow Sofics on LinkedIn, Facebook or Twitter to stay up-to-date about our next articles, tutorials and videos.
SOFICS - Solutions for ICs 