Adapting Diode triggered SCRs (part 2)


In the first part [Link] we discussed about different ESD protection approaches and introduced the SCR based protection. Even though proper on-chip ESD protection is critical to IC performance, it is not always straightforward to consider it early on in the IC design process.

In this article, I wish to introduce you to how we can use diode triggered silicon controlled rectifiers (DTSCRs) for on-chip ESD protection. I will explain how its 3 main parameters – trigger voltage, holding voltage and failure current – can be tuned in order to protect ICs with very different characteristics.

As its name implies, a DTSCR is constructed by combining an SCR with diodes to form a versatile circuit whose properties can be tuned at will to suit the requirements of the IC/interface which needs to be protected. Figure 1 illustrates the possible configurations for a DTSCR. A and C represent the SCR Anode and Cathode respectively.

basic DTSCR structure
Figure 1: Diode triggered SCR using trigger tap G1 (left) or using trigger tap G2 (right).

Controlling the triggering voltage (Vt1)

Typically, an SCR is triggered if the G1 node is biased high or the G2 node is pulled lower than the Anode. The SCR trigger voltage (Vt1) is its first important parameter which can be tuned. In the standalone (no trigger diodes) case, Vt1 is determined by the SCR’s material parameters and fabrication and is above the Nwell-Pwell (G2-G1) breakdown voltage.

This may not always suit the application at hand; for example, circuits in a 180nm CMOS running at 1.8V supply voltage (Vdd) cannot be protected with an standalone SCR that turns on above 15V. Fortunately, we can adapt the Vt1 trigger voltage by using diodes positioned close to the SCR.

We can trigger the DTSCR by controlling whether the G1 – C or A – G2 junction is forward biased. We can achieve either outcome by adding an appropriate number of triggering diodes. However, there is an important difference when we compare triggering from G2 to triggering from G1.

The A – G2 junction counts as a triggering diode due to the fact that the Nwell is isolated from the Psubstrate. For G1 triggering, we do not have the same effect because there is a direct connection to the ground (Psubstrate). Consequently, it is possible to achieve the same Vt1 by using n diodes applied to G1 or n-1 diodes applied to G2.

Trigger voltage engineering
Figure 2: Trigger voltage engineering for a G2 triggered DTSCR. The TLP I-V characteristic shows that increasing the number of trigger diodes leads to an increase in the triggering voltage.

Accordingly, if we consider for convenience Vt1 engineering for a DTSCR triggered from G2. The transmission line pulsing (TLP) I – V characteristics for DTSCR’s with different numbers of trigger diodes shows increasing the number of triggering diodes leads to an increase in Vt1 (see figure 2).

Controlling the holding voltage (Vh)

A DTSCR’s holding voltage can be controlled by including diodes in series with the A – G2 junction as shown in figure 3 below. This arrangement is usually necessary to provide latch-up immunity during the IC’s normal operation by ensuring the holding voltage (Vh) is higher than the IC’s power supply (Vdd).

We also note that the holding diode also functions as a trigger diode. As we can see in figure 3, deleting a trigger diode and adding a holding diode results in an increased Vh (increase of about 1V) but with the same Vt1. This DTSCR with one trigger diode and one holding diode can be used as an ESD clamp for an IC with 1.8V power supply. 

Holding voltage engineering
Figure 3: DTSCR with holding diode. TLP I-V characteristic showing how the holding diode increases the holding voltage of the DTSCR.

Controlling the failure current (It2)

The final DTSCR parameter which can be adjusted to suit the situation at hand is its failure current (It2). The ESD robustness requirements can differ strongly for various applications. Most IC interfaces are fine with a 2kV HBM level, about 1.3A of TLP (It2). However, some applications like HDMI or USB interfaces require a much higher level of 8kV HBM or more. The failure current of the SCR device can be easily changed by making the device larger. 

Failure current engineering
Figure 4: TLP failure current It2 (vertical axis) of SCR devices with different widths. There is a linear relationship allowing an easy, deterministic way to adapt the SCR clamp for every requirement.

Discussion and examples

So far, we have looked at the design of DTSCR-based ESD clamps for CMOS ICs in a general context. We have seen how we can design the DTSCR behavior by altering its trigger voltage, holding voltage and failure current. In what follows, we move on to examining some practical examples. In table 1, we list five DTSCR’s and their characteristics for ICs with 2 kV HBM ESD specification.

We cover ESD clamps for several voltage domains; 0.9V, 1.2V, 1.5V and 3.3V. For the trigger and holding voltages, we see a straightforward correlation i.e. more trigger (respectively holding) diodes leads to a higher Vt1 (respectively Vh). The SCR clamps are all designed for the same ESD robustness level and thus the failure current does not change a lot.

Table 1: Examples of DTSCRs for practical applications.

A complete examination of all the possibilities accessible to DTSCRs would be a very involved exercise and is beyond the scope of this article. In this write up, I just tried to give the reader an idea of the basics. There are many other aspects which need to be taken into account for practical devices.

More information?

  • First part of the article: LINK
  • Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxides. LINK
  • Speed Optimized Diode-Triggered SCR for RF ESD Protection of Ultra-Sensitive IC Nodes in Advanced Technologies. LINK
  • Improved Turn-on Behaviour in a Diode-Triggered Silicon-Controlled Rectifier for High-Speed Electrostatic Discharge Protection. LINK

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