Adapting Diode triggered SCRs (part 2)

Introduction

In the first part [Link] we discussed about different ESD protection approaches and introduced the SCR based protection. Even though proper on-chip ESD protection is critical to IC performance, it is not always straightforward to consider it early on in the IC design process.

In this article, I wish to introduce you to how we can use diode triggered silicon controlled rectifiers (DTSCRs) for on-chip ESD protection. I will explain how its 3 main parameters – trigger voltage, holding voltage and failure current – can be tuned in order to protect ICs with very different characteristics.

As its name implies, a DTSCR is constructed by combining an SCR with diodes to form a versatile circuit whose properties can be tuned at will to suit the requirements of the IC/interface which needs to be protected. Figure 1 illustrates the possible configurations for a DTSCR. A and C represent the SCR Anode and Cathode respectively.

Controlling the triggering voltage (V_t1)

Typically, an SCR is triggered if the G₁ node is biased high or the G₂ node is pulled lower than the Anode. The SCR trigger voltage (V_t1) is its first important parameter which can be tuned. In the standalone (no trigger diodes) case, V_t1 is determined by the SCR’s material parameters and fabrication and is above the N_well-P_well (G₂-G₁) breakdown voltage.

This may not always suit the application at hand; for example, circuits in a 180nm CMOS running at 1.8V supply voltage (V_dd) cannot be protected with an standalone SCR that turns on above 15V. Fortunately, we can adapt the V_t1 trigger voltage by using diodes positioned close to the SCR.

We can trigger the DTSCR by controlling whether the G₁ – C or A – G₂ junction is forward biased. We can achieve either outcome by adding an appropriate number of triggering diodes. However, there is an important difference when we compare triggering from G₂ to triggering from G₁.

The A – G₂ junction counts as a triggering diode due to the fact that the N_well is isolated from the P_substrate. For G₁ triggering, we do not have the same effect because there is a direct connection to the ground (P_substrate). Consequently, it is possible to achieve the same V_t1 by using n diodes applied to G₁ or n-1 diodes applied to G₂.

Accordingly, if we consider for convenience V_t1 engineering for a DTSCR triggered from G₂. The transmission line pulsing (TLP) I – V characteristics for DTSCR’s with different numbers of trigger diodes shows increasing the number of triggering diodes leads to an increase in V_t1 (see figure 2).

Controlling the holding voltage (V_h)

A DTSCR’s holding voltage can be controlled by including diodes in series with the A – G₂ junction as shown in figure 3 below. This arrangement is usually necessary to provide latch-up immunity during the IC’s normal operation by ensuring the holding voltage (V_h) is higher than the IC’s power supply (V_dd).

We also note that the holding diode also functions as a trigger diode. As we can see in figure 3, deleting a trigger diode and adding a holding diode results in an increased V_h (increase of about 1V) but with the same V_t1. This DTSCR with one trigger diode and one holding diode can be used as an ESD clamp for an IC with 1.8V power supply. 

Controlling the failure current (I_t2)

The final DTSCR parameter which can be adjusted to suit the situation at hand is its failure current (I_t2). The ESD robustness requirements can differ strongly for various applications. Most IC interfaces are fine with a 2kV HBM level, about 1.3A of TLP (I_t2). However, some applications like HDMI or USB interfaces require a much higher level of 8kV HBM or more. The failure current of the SCR device can be easily changed by making the device larger. 

Discussion and examples

So far, we have looked at the design of DTSCR-based ESD clamps for CMOS ICs in a general context. We have seen how we can design the DTSCR behavior by altering its trigger voltage, holding voltage and failure current. In what follows, we move on to examining some practical examples. In table 1, we list five DTSCR’s and their characteristics for ICs with 2 kV HBM ESD specification.

We cover ESD clamps for several voltage domains; 0.9V, 1.2V, 1.5V and 3.3V. For the trigger and holding voltages, we see a straightforward correlation i.e. more trigger (respectively holding) diodes leads to a higher V_t1 (respectively V_h). The SCR clamps are all designed for the same ESD robustness level and thus the failure current does not change a lot.

Voltage Rating	Trigger Diodes	Holding Diodes	Holding Voltage	Triggering Voltage	Leakage	Failure Current
0.9V	1	1	2.0V	2.0V	10pA	1.4A
1.2V	2	1	2.0V	2.9V	11pA	1.3A
1.5V	3	1	2.0V	3.8V	15pA	1.4A
1.5V	3	2	3.1V	4.8V	2pA	1.3A
3.3V	4	3	3.9V	5.8V	8nA	1.3A

A complete examination of all the possibilities accessible to DTSCRs would be a very involved exercise and is beyond the scope of this article. In this write up, I just tried to give the reader an idea of the basics. There are many other aspects which need to be taken into account for practical devices.

More information?

• First part of the article: LINK
• Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxides. LINK
• Speed Optimized Diode-Triggered SCR for RF ESD Protection of Ultra-Sensitive IC Nodes in Advanced Technologies. LINK
• Improved Turn-on Behaviour in a Diode-Triggered Silicon-Controlled Rectifier for High-Speed Electrostatic Discharge Protection. LINK