Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 1)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

Introduction

Semiconductor processes get more expensive at every new, denser technology node [1]. It has always been like this, but the trend seems to be persisting exponentially due to increased complexity (mask resolution, materials, equipment like EUV) for the most advanced process technology (Figure 1).

There is an interesting shift at the 22nm-16nm range, where the process stopped being planar CMOS and moved to FinFET. Yet, as the most advanced nodes have moved away from this range, the wafer cost of 16nm to 22nm differ less than 10%. Moreover, SOI has moved to 22nm as well, such that in the 16nm-22nm range for a similar wafer cost, 3 options are available: (1) 22nm CMOS, (2) 22nm SOI and (3) 16nm FinFET.

Though process selection for a new IC design is not done based on the ESD characteristics of the process, it is interesting to compare technologies from this perspective and see what the consequences are selecting one over the other, looking at it from an ESD viewpoint.

Approach

In the paper, different ESD concepts are evaluated and compared for the three process options. The comparison is based on these aspects:

• Construction: what is the cross-section in the given process option?
• Applicability for ESD protection
• ESD characteristics: voltages, amount of current in terms of perimeter and area.

Device construction

The basic transistor construction is different for the 3 process options. Comparing the device construction (Figure 2), one can see that the plain CMOS technology just has two N+ regions, drain and source, in an P-type well or substrate. Of course, a gate is on top of the device channel. Looking at SOI, a buried oxide (BOX) shields the transistor p-type body from the substrate. This has major consequences for ESD (see below). The FinFET cross-section essentially consists of small stripes (fins) for drain-body-source in parallel, with the gate wrapped around the body for each section. This of course confines the body volume significantly, which enables better control of the channel, but also has a major influence on ESD properties. Note that the transistor body still resides in the substrate. There is no electrical isolation, as is the case for SOI.

ESD protection devices

Looking at an overall picture of different ESD strategies (Figure 3), one can see that the diode is used in most cases as the primary ESD protection device in the I/O’s. Also between grounds (not depicted), anti-parallel diodes are used a lot. Therefore, the diode will be the first device discussed below. A gate-grounded NMOS (ggNMOS) is frequently used as secondary (CDM) protection for input gates. Furthermore, self-protective drivers are still a popular option for output protection. In more mature nodes like 0.25um CMOS, ggNMOS transistors were also used for power protection, but in more advanced nodes, the narrower ESD design window (more below) does not allow that. Silicon Controlled Rectifiers (SCR) are more popular today, not just for power lines, but also for I/O protection, either to circumvent the reliance on bus resistance [2], or to deal with overvoltage tolerant specifications, where a diode between pad and supply is not allowed [3]. SCRs will be the third device in the study. Lastly, the BigFET, where a MOS device is connected between the power rails, is discussed. The large MOS device is driven in conduction mode by a timing circuit that detects ESD events [4-6].

ESD design window

Before discussing the details of the protection devices, it is important to look at the ESD design window. An ESD design window is a voltage specification, which has the supply, typically augmented with 10% safety margin, as the minimum value. ESD devices should behave as a high impedance below this minimum value.

The maximum value in the ESD design window is defined by the failure voltage, during ESD events, of the functional circuit itself. It is determined in an ESD relevant time domain, for instance using a Transmission Line Pulser (TLP) [7-9]. For effective ESD protection, the voltage drop across the entire ESD current path must stay below the maximum value.

Though deriving the correct voltage for a complete I/O circuit requires expertise beyond the scope of this paper [10], two measurements stand out: the failure voltage of the gate oxide, and the failure voltage of an output driver (drain to source).

It can be seen from Figure 4 that the gate failure voltage (red line) decreases with advancement of the technology at a much higher pace as the decline in supply voltage (blue line), which means that the voltage drop over the ESD circuitry must be reduced. The back-end (metal connections, via layers) becomes weaker as well [11]. The metal wiring of the ESD protection devices becomes a field of expertise by itself.

Comparing the failure voltage of a single NMOS output driver (Figure 5), it is clear that the CMOS option is significantly higher than SOI and FinFET cases. In the SOI process we also noticed a lot of variation (more than 1 V) in the failure voltage for different device layout options like Vth implant.

Summary

In this article we compared different process options (Bulk CMOS, SOI and FinFET). The intrinsic robustness of the different options is influenced by the device cross sections. In the second part (Link) of the article the different ESD device types (Diode, NMOS, SCR and BigFET) are compared in more detail.

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References

1. Wafer price for advanced nodes – https://www.techspot.com/news/86813-analysts-believe-single-tsmc-5nm-wafer-costs-17000.html
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8. Keppens, Bart, “Contributions to standardization of transmission line pulse testing methodology”, Proc. Of the EOS/ESD Symposium 2001
9. Barth, John, “TLP Calibration, Correlation, Standards, and New Techniques”, 2002
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11. Sorgeloos B. et al.,“The impact of a decade of Technology downscaling”, 2012 Taiwan ESD and reliability conference (Link)
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15. Keppens B, et al., “Concept for Body Coupling in SOI MOS Transistors to Improve Multi-Finger Triggering”, 2006 EOS/ESD Symposium (Link)
16. Fukuda Y, et al.,“Solving the problems with traditional Silicon Controlled Rectifier (SCR) approaches for ESD”, 2008 RCJ Symposium (Link)
17. Avery, L., “Using SCRs as Transient Protection Structures in Integrated Circuits”, EOS/ESD 1983
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