More and more companies are turning to advanced semiconductor packaging. This trend has an effect on ESD protection. Earlier in 2021, Sofics submited a paper for the IP-SOC USA conference. The abstract is shown below.
The conference was hosted virtually. The presenation was recorded and can be viewed here.
The slides can be browsed below.
A growing number of semiconductor applications are turning to 2.5D and 3D integration. It is important to consider Electrostatic Discharge (ESD) protection early in the design phase because there are new ESD challenges but also opportunities for cost reduction.
In this hybrid integration approach there are 2 types of chip interfaces. Similar to the old (one die in one package) there are chip interfaces that connect the electrical die interfaces to the outside world. Secondly, there are now interfaces that stay within the package are also called ‘die-2-die’ interfaces. During the presentation we touched on 3 aspects that are different for both interface types: ESD protection, signal voltage and layout considerations
Sofics has supported several projects in the past where die-2-die interfaces required a unique, custom ESD or I/O solution. Some of our solutions used in the past are a perfect match for die-2-die interfaces. Our focus on local ESD clamp solutions is useful for protecting die-2-die interfaces. Our ability to scale the ESD robustness up/down ensures our customers can easily enjoy the benefit of a smaller ESD solution with strongly reduced parasitic capacitance.
Contact us f you like to discuss your own IC project.