Protection of CMOS output drivers

Every computer chip needs on-chip ESD protection at its interfaces. Integrated circuits have different kinds of interfaces. This article discusses approaches to protect output drivers. The most optimal solution depends on the ESD requirement, the intrinsic robustness of the process, the output signal voltage, the signal speed requirements and tolerated leakage.

CMOS inverter style output driver. The most sensitive element during ESD stress is the NMOS driver.

Different options

This article compares different options for output drivers, focused on the NMOS transistor because that is the most sensitive part and is easily damaged during ESD stress. The examples are based on a 130nm CMOS process. In the examples the output driver is designed with 4 fingers of 20um each for a total perimeter of 80um.

The NMOS is harder to protect during ESD because it typically has a snapback behavior as shown below. The clamping or holding voltage (Vh) is lower than the trigger voltage (Vt1).

TLP curve for a (thick oxide) NMOS transistor in a 180nm CMOS process.

That makes it hard to ensure all the device fingers are sharing the ESD current. PMOS transistors in most CMOS processes do not have a snapback which means that the ESD current is easily shared across all device fingers.

Option 1: fully silicided drivers – reference

If electrostatic discharge events would not exist, the IC designer would be able to just design the output driver for optimal performance during functional operation. The design can use minimum design rules. The perimeter is then defined to achieve the required drive strength. In this example we use a total perimeter of 80um (4 times 20um). This option has low parasitic capacitance and low ON-resistance, ideal for a fast driver. The silicon footprint is also small. In 130nm CMOS it is about 200um², including a guard ring.

Layout of a NMOS in 130nm CMOS (4 fingers of 20um). Total area of about 200um²

Unfortunately this design is easily damaged during ESD stress. In mature CMOS processes such a layout style could be OK but in advanced CMOS and FinFET technology NMOS transistors without silicided blocked drains (option 3) are damaged right after snapback. The parasitic bipolar NPN is turned on in a single device finger and shunts all the ESD current until it breaks.

In the case the NMOS transistor is not damaged at snapback the ESD failure current is rather low for the 80um total perimeter, e.g. less than 300mA.

Option 2: fully silicided drivers, additional ‘dummy fingers’

Similar to option 1, the layout is designed with minimum design rules. The total perimeter is increased to 400 um (20 fingers). 16 of the device fingers are so-called ‘dummy fingers’. They are not required for the normal operation. Theses 16 additional fingers are just added to increase the ESD protection capability. Because the layout is still using the minimum design rules the parasitic capacitance and resistance is reasonable. The silicon footprint is obviously larger compared to option 1 at about 550um².

Layout of a NMOS in 130nm CMOS (20 fingers of 20um). Total area of about 550um²

While this layout style can increase the ESD robustness in some older processes, it may still be lower than expected and it will be hard to reach the 2kV HBM performance consistently in advanced technology.

Option 3: Foundry ESD rules: silicide blocked drains

Most foundries suggest to increase the drain contact to gate spacing and also recommend to remove the silicide on the drain (silicide block or RPO mask). This can make sure all device fingers are triggered during ESD stress through micro and macro ballasting. The total perimeter is set at 400um (20 fingers of 20um).

Layout of a NMOS in 130nm CMOS (20 fingers of 20um). Larger drain contact to gate spacing and silicide is blocked at the drain area. Total area of about 1700um²

The ESD performance is certainly improved compared to option 1 and 2 but due to the larger design rules and additional silicide block layer the silicon footprint is really large (about 1700um²). Also the parasitic capacitance and on-resistance during functional operation are much higher. The maximum switching speed is reduced.

Option 4: Secondary protection

If the design can tolerate a resistance (example 50 to 100 Ohm) between the pad and the driver, the secondary protection approach can provide an area saving compared to Option 3. In this case the majority of the ESD current is shunted through the primary protection. Only a fraction of the ESD stress flows through the NMOS transistor.

The primary protection consists of a dual diode ESD protection. The output driver perimeter can be kept at the minimum 80um. To ensure this small driver can shunt (a fraction) of the ESD current the foundry ESD rule (Silicide blocked, larger drain area) is used for the layout. The total silicon footprint is about 900um².

Layout of a NMOS in 130nm CMOS (4 fingers of 20um) as secondary protection and ESD diodes for the primary protection. Total area of about 900um²

The ESD robustness of this approach is certainly better than the option 1 and 2. The area saving compared to option 3 is clear. The main issue is the resistance. For slow interfaces and low drive currents, it is OK but frequently output drivers cannot tolerate additional resistance in the signal path.

Option 5: Parallel local protection

In this case an additional ESD device is added in parallel to the output driver. The main principle is to provide another current path for the entire ESD current. The NMOS transistor does not shunt any ESD current. This means the NMOS layout can default back to option 1: minimum perimeter (80um), minimum design rules and fully silicided. This is beneficial for the normal operation: the on resistance is as low as it can be – ideal for fast signals.

Of course an additional ESD device is added. In this example a Sofics proprietary Diode Triggered SCR device (Link) is added. The total silicon footprint is then about 1300um².

Layout example for a combination of a small NMOS (4 fingers of 20um, minimim design rules) and a diode triggered SCR. Total area is about 1300um²

SCRs have a lot of benefits. For the same ESD performance 5 times less junction area is required, leading to low parasitic capacitance for this option, about 150fF more than the reference (option 1) while the ESD robustness is much higher.

In most high voltage processes (BCD, DMOS) option 5 is the only reliable approach. Based on characterization of many such processes Sofics engineers decided to never rely on ESD current through high voltage (5V and up) NMOS transistors, not even in a secondary protection approach (option 4). Several foundries claim that they have a layout style that is ESD robust however, that is typically based on a limited number of ESD stress pulses. The main issues for NMOS based ESD protection in high voltage technologies are summarized in our peer-reviewed paper on solutions for HV interfaces (link).

Comparison and conclusion

The table below compares the 5 options on 4 aspects (silicon footprint, Capacitance, resistance, ESD protection level).

Clearly, the typical foundry recommendation (larger drain area, silicide blocked drains, additional dummy fingers) is the worst option. It can reach the desired ESD protection but the required silicon footprint is excessive. Moreover, the parasitic capacitance is rather high.

Of course options 1 and 2 yield better functional performance but typically fail at a much lower ESD level. Both option 1 and 2 can be improved somehow through the use of a DeepNwell layer. By isolating the body of the transistor from the substrate it is easier to ensure multi finger triggering. Additionally one could add a 1k Ohm resistance to ground from the gate for the dummy transistor fingers (option 2). This will also reduce the trigger voltage. Some processes have an ESD implant option that can further improve the ESD robustness of options 1-3. An adapted pre-driver could provide a dynamic (higher) gate bias during ESD stress but most I/O designers do not like to adapt the pre-driver design. It is hard enough to meet slew rate and programmable drive strength requirements..

Sofics has developed several innovative layout styles that can improve the ESD robustness of NMOS transistors in CMOS process technology. The Back-end-ballast technique (link), Active Area Ballast layout (link) and multi-finger-trigger schemes (link) strongly improved the ESD robustness per area compared to the silicide blocked layout style (option 3).

As mentioned in the introduction, the optimal solution really depends on the requirements. If your circuit can tolerate more than 50 Ohm resistance at the output drivers, option 4 is probably the best. In all other cases option 5 is the best way forward.

Contact us to discuss ESD protection for your next chip project.

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Published by 32bartkeppens

Sofics provides solutions for the ESD/EOS/EMC robustness of integrated circuits. We have a 20+ years track record, supporting 100+ fabless companies worldwide with on-chip ESD protection and custom/specialty Analog I/O’s and PHY’s. Solutions in CMOS, BCD, FDSOI and FinFET technology are available off-the-shelf Since 2019: Sofics: Responsible for business Development worldwide 2009 - 2019: Sofics: Technical marketing director 2006 - 2009: Sarnoff Europe: Support for business development 2002 - 2006: Sarnoff Europe: Solving ESD related issues for customers worldwide 1996 - 2002: Imec, Belgium: Member technical staff Topics: on-chip ESD protection, ESD analysis, non-volatile memories 1996: Engineering degree in electronics from Groep T, Leuven, Belgium (co-) authored more than 40 peer-reviewed published articles.

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