The ESD design window concept

The ESD design window is a concept used by IC designers to define the requirements for the ESD protection devices. This article provides information on the different aspects like robustness, effectiveness and transparency of ESD devices.

Typical ESD event: touching a door knob during a dry day


Electro Static Discharge (ESD) is the sudden discharge of a charged object. It is characterized by high current levels (1 to 10 ampere), short time (less than 1us) and fast rise time (less than 10ns).

ESD is an important issue in the semiconductor world. The events can occur during wafer fabrication, testing, dicing, assembly and functional use of semiconductor devices. ESD stress can damage Integrated Circuits (IC) in several ways. In advanced semiconductor fabs engineers try to prevent charge build-up with ionizers, grounding methods and dissipative materials to transport chips.

However, for absolute certainty, IC designers should include so-called on-chip ESD protection devices at the various chip interfaces (inputs, outputs, power pads).

Simplified schematic of an integrated circuit with inputs, outputs and core circuit. The ESD protection devices (blue/green) are included at various places in the chip design.

The industry uses many different ESD devices because every case is different. For instance an on-chip solution for ESD stress between the ‘IN’ pad and the ‘VSS’ pad (figure above) has different requirements compared to stress between ‘VDD’ and ‘VSS’. In the first case the ESD device must prevent breakdown of a (thin) gate oxide (Gate-Source NMOS transistor). In the second case the ESD device should shunt ESD current from VDD to VSS below the failure voltage of a complete functional core circuit. Most semiconductor foundries provide an I/O library and ESD protection solutions to their customers. These libraries cover the typical applications with regular requirements. However, in many cases the IC designer needs a custom solution.

Example: ESD protection for an input interface

An input circuit, simplified in the figure below (left side), needs an ESD protection clamp. To define the requirements for the ESD clamp device we have to understand the failure voltage of the circuit. We can use a TLP tester to measure the maximum voltage (right side). The failure voltage of the gate oxide is about 5.3V for this example (thin oxide transistor in a 130nm SOI technology).

Simplified schematic for an inverter input. With a Transmission Line Pulse system, short (100ns), rectangular pulses with a varying voltage level are subjected to the input to emulate ESD stress events. On the right side the TLP curve (blue dots) is plotted. At 5.3V across the Gate-Source of the NMOS transistor the gate oxide breaks down. This is clearly shown by a sudden increase of the leakage (red curve).

An ESD device is a switch

Frequently, ESD protection devices are switches. During normal operation the switch is an open circuit with high impedance. When an ESD event occurs the switch should close, to provide a low resistive path for the ESD current.

ESD switch device between IN and VSS. During functional operation the switch is open. During ESD it should be closed.

Such a switch would be able to protect the gate oxide in the example above. ESD current is shunted at low voltage, through the switch, protecting the gate-source oxide. Once the ESD event is gone, the switch can re-open and the input inverter can receive signals again.

It would be nice to have an ideal switch as ESD protection. However a realistic ESD switch has a number of non-ideal properties or limitations.

  • ESD devices have an influence on the normal circuit operation. The device introduces leakage, adds resistance in the functional current path and adds parasitic capacitance, influencing the signal integrity for fast signals
  • For a real ESD device the voltage has to rise above a ‘trigger voltage’ before it is activated.
  • The ideal switch shunts ESD current at 0V. However, there is always a voltage drop across actual ESD devices because they have a clamping voltage and non-zero on-resistance.
  • Real ESD switches have a finite turn-on time. This is especially important for fast ESD events like Charged Device Model or IEC 61000-4-2 stress.
  • An ideal switch can shunt an infinite amount of current. However, real devices have a certain failure current.
  • ESD devices have a certain silicon footprint.

The ESD design window concept helps us to define required properties of the ESD device. This makes it easier to look for the optimal solution. There are 3 main definitions: Transparency, Robustness and Effectiveness.

For the second part of the article we refer to the IV curve of a typical ESD clamp device. We use a Transmission Line Pulse (TLP) test system to create this IV curve for the ESD clamp devices.

Basic IV curve for an ESD clamp device. The clamp has a trigger voltage (Vt1), a clamping/holding voltage (Vh), an on-resistance (Ron) and a failure current level (It2).

Definition 1: Transparency

As mentioned above, the ESD clamp device influences the circuit operation. The IC designer should think about the maximum tolerated leakage, parasitic capacitance and resistance from the ESD device. These requirements can be different for each interface. Typically the leakage of the ESD clamp depends on the temperature. The parasitic capacitance can depend on the frequency and signal voltage.

The switch should be an open circuit during the functional operation. It is important to understand the maximum voltage of normal operation signals. If the interface operates at 5V, the switch should stay open well beyond 5V.

  • For rail/power clamps we define the following requirements
    • Trigger voltage Vt1 > Vdd voltage + 50% to pass burn-in/latch-up tests
    • Holding/clamping voltage Vh > Vdd + 10% to prevent latch-up.
  • For ESD protection of I/O interfaces we use similar targets
    • Trigger voltage Vt1 > maximum signal voltage + safety margin
    • If possible we should also increase the holding voltage beyond the maximum signal voltage to prevent latch-up.
Requirements for the ESD power clamp to insure transparency

Definition 2: Robustness

The ESD protection clamp needs to be robust. It should be able to handle a certain amount of ESD current. This current level is the ESD current level specification.

The ESD current level specification defines the robustness of the ESD clamp. The ESD clamp should be able to shunt more current than the ESD specification.

Unfortunately most ESD test standards are defined in voltage. For instance the typical value for the HBM standard, required for most chips, is defined as 2000 V. For the HBM standard we define the peak current as “0.667A for every 1000V of HBM”. For 2kV HBM it means that the ESD clamp should be able to shunt more than 1.33A of current.

A simple correlation to (peak) current is not always possible. For CDM for instance, the peak current depends on the package type and size. More info is available in another article (link). In the CDM case we also use another TLP system (VF-TLP) to measure the IV curve of the ESD clamp. Typically the robustness of an ESD clamp is higher for ESD stress pulses with shorter pulse duration (e.g. 5ns versus 100ns).

Sofics experts can help to define the right current level for your specific ESD requirements.

Definition 3: Effectiveness

A third aspect is effectiveness. An ESD clamp can be robust enough and transparent but it also needs to protect the functional circuit during stress events. We therefore define the maximum voltage of the clamp device: Vmax. Think about the example at the start of this article. The gate oxide of the input circuit fails at 5.3V. The ESD clamp needs to shunt the ESD current while keeping the voltage below 5.3V. We tend to take a safety margin of 10% to cover process variations of the failure voltage.

The ESD design window for a power clamp. The clamp voltage should remain under the maximum voltage defined by the failure voltage of the functional circuit in parallel to the ESD device.

Clearly, the maximum voltage ‘vmax’ depends on the functional circuit. It also depends on the process technology. For instance the gate oxide breakdown voltage in 16nm FinFET is much lower than the gate breakdown in 0.25um CMOS technology. Sofics experts have measurement data on more than 50 processes to help you assess the failure voltage of your circuit. A summary paper is available on our website (link). Another paper provides examples on setting the maximum voltage for more complex circuits (link).

There are some aspects not covered in the simplified ESD design window. For instance, during fast ESD event like CDM, certain clamps may respond slowly, causing a voltage overshoot. Sofics uses the VF-TLP test system to assess the transient voltage overshoot during short pulses with fast rise time (200ps or faster).


The ESD design window defines the requirements for the ESD protection clamps. ESD clamps should be invisible during functional operation (‘transparent’). The clamp should be able to shunt enough current (‘robust’) while limiting the voltage below the failure voltage of the circuit (‘effective’). IC designers should create an ESD design window for every stress combination.

Contact us if you need support for your next IC design.

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Published by Bart Keppens

Chief Business Development at Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog IOs and on-chip ESD protection. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. Our technology has been characterized on 11 foundries including advanced nodes at TSMC, UMC, GF, Samsung Foundry.

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