ESD protection solutions for space applications

We frequently get questions about the applicability of our ESD and I/O solution IP for space applications. There are several aspects that need to be checked before electronics can be used in such harsh environments. Semiconductor devices that are used at high elevation or in space need special attention during the design phase. Sofics technology has been used for a number of aerospace projects. In this article we provide more background and some example cases.

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Low power solutions

Frequently space applications need to harvest energy from the sun with solar panels. The engineers also have to consider that the solar panels are not always active. When the device is far away from the sun or in the shadow of a planet or moon, a battery takes over. It is clear that this limits the total available energy for the electronic circuits. IC designers use low-power designs and rely on techniques to shut-down parts of the circuit when these are not relevant.

While the power consumption from interface (I/O) circuits and ESD devices typically is just a fraction compared to the power consumption of the functional circuits there is ample opportunity to gain more battery life time. There is a large difference between stand-by leakage of traditional ESD solutions and dedicated low-leakage alternatives like those provided by Sofics. Instead of a leakage of 0.1uA at 3.3V (traditional rail clamp) it could be 100x to 1000x lower (sub nA for Sofics power clamps).

Sofics technology provides an opportunity to drastically reduce the leakage from ESD protection clamps. The leakage can be 100x and sometimes 1000x lower.

For the circuits that are frequently powered down designers should also replace the RC-triggered rail clamps with voltage level triggered alternatives. The RC-detection is fired every time the circuit is turned-on, momentarily leaking charges from the battery to ground through the large BigFET transistor.

Extended temperature range

If you think about satellites orbiting the earth, it is easy to see that there is a big temperature difference between when the satellite is in the shadow of the earth and when it is in direct sunlight. A difference between cold/hot can be 300°C or more. On the moon surface the temperature range is between -200°C and +200°C. The constant temperature fluctuations are causing issues for chip packages.

The electronic circuits inside the package must be able to handle this large temperature range too. ESD devices typically have a much higher leakage at high temperature. Another reason why IC designers should select low-leakage ESD concepts.

Radiation hard electronics

The enhanced radiation can degrade circuit performance or even damage some circuits for instance during single event latch-up.

Radiation can alter the contents of memory blocks, which may change the state diagram of the software causing it to misbehave. Designers sometimes integrate 3 identical circuits and use a voting system where the majority (2 out of 3) rules when the results are different.

Radiation can degrade the performance when charges are trapped inside oxide layers in the integrated circuits. These trapped charges can for instance drastically change the Vth level of MOS transistors. This could lead to increased leakage or lock the transistor in one mode (open/closed). Designers can use a different layout style for the transistors or rely on bipolar devices.

Advanced CMOS processes typically have different MOS transistors types. (1) There are thin-oxide core transistors for low voltage operation. The main logic circuit is built with those transistors. Foundries also offer another, (2) thick-oxide transistor type that is used for interface circuits and I/Os. Frequently these thick-oxide transistors are more vulnerable for total dose irradiation because that oxide has a higher defect density and thus more easily traps charges. Unfortunately, most foundries only have I/O circuits and ESD protection clamps built with thick-oxide transistors. Sofics has delivered a number of rad-hard I/O libraries for 1.2V applications in e.g. TSMC 65nm, TSMC 130nm, GF 130nm and TSMC 28nm technology.

Besides degradation, radiation can also cause single event upsets. Such upsets can turn on ESD devices while the functional circuit is operating, interrupting the function and potentially causing damage through latch-up. Designers should use latch-up robust ESD clamps with a high clamping voltage. For high voltage applications this leads to a larger silicon footprint. In some (non-space) applications designers reduce the silicon area when they use ESD circuits with low clamping voltage. They prevent latch-up with layout techniques that increases the trigger current for the ESD clamp device. Additionally they use guard bands and a large distance between the ESD device and the functional circuits. This prevents that noise is coupled to the ESD device. However, all these measures are futile when a high energetic particle hits the ESD clamp itself. Clearly, for space applications, the clamping voltage should be high enough.

Cold-spare

Earlier in the article it was already mentioned that circuit designers sometimes include 3 identical circuits to detect single event upsets and prevent malfunction. Another technique is to use a back-up circuit when the main/primary circuit fails: a “cold-spare”. A spare or 2nd circuit that is not powered, hence cold.

It is common practice to route the I/O signals to both primary and back-up circuits and only provide a switch for the power to select between the primary and the back-up circuit. This has an important consequence for the I/O pads.

Traditional ESD solution for analog I/Os: Dual diode ESD protection. The diode-up between Input and Vdd causes problems for cold-spare interfaces.

The traditional ESD protection for analog I/Os is built with 2 diodes. A diode between Vss and the I/O-pad (diode down) and another one from I/O pad to Vdd (diode up). For cold-spare applications this dual diode concept cannot be used because the ‘cold’ circuit will get charged up through the diode up. For these cold-spare I/Os another protection approach is required. Sofics has provided small area, low-leakage local protection clamps on several process technologies to enable this. There are several other techniques, described in another article (link)

Local ESD protection for cold-spare interfaces.

Case study – Arquimea.

Several years ago, we cooperated with Arquimea on high reliability ICs for the European Space Agency. Arquimea is an Aerospace and Defense qualified supplier and fabless design house focused on analog and mixed signal microelectronics for high reliability applications with expertise on radiation mitigation by design. The European Space Agency (ESA) asked Arquimea to create several circuits including LVDS circuits running on extended signal voltages, beyond the voltage domains available for the standard IOs in the IHP SiGe BiCMOS 0.25um process. One of the critical design parameters was the target to protect the ICs against severe electrostatic discharge (ESD) stress of about 8kV HBM. The project started with a study of the IHP process to understand the opportunities for ESD protection as well as the weaknesses (sensitive devices) and the circuits to be protected. The parties then designed different blocks for verification on the IHP process.

  • A dedicated test chip with several ESD clamps and diodes, all scaled to reach 8kV HBM
  • Functional sub-circuits, protected with the most appropriated ESD clamps
  • An Octal LVDS repeater for fast communication where the interfaces were protected by the ESD clamps.

The measurement results showed that the different ESD clamp and diode cells reach more than 5A TLP. The example below shows analysis on the bidirectional clamp used for the -4V to 5V interface that can be used in cold sparing interfaces. The designs were later used in a satellite, circling earth.

TLP results from the ESD devices on the test chip on the IHP SiGe BiCMOS 0.25um process. The ESD robustness was scaled up to 8kV HBM.

Case study – Rad-hard devices

Another customer asked our help to ensure the ESD protection circuits are immune against single event upsets. The Sofics proprietary SCR on-chip ESD protection devices were used in a number of programmable chips for aerospace applications in 65nm and 28nm CMOS. Our customer made radiation measurements in a dedicated facility to understand the level of immunity against single event latch-up. The products reached up to 120 LET, passing their requirement.

Other applications with similar requirements

Some of the aspects that are required for space applications like radiation-hard concepts can be used in more down-to-earth applications. Electronics with a high tolerance against radiation are also convenient in nuclear facilities, medical imaging (finding broken bones?) or security imaging applications (airport scanners) and in a large hadron collider for fundamental particle research at CERN for instance. In those applications the focus is prevention of degradation during long periods of radiation.

Further reading

A nice article about challenges for Electronic circuits in Space applications: (link).

Our partner Imec in Belgium has a whole solution set for radiation hard applications: The DARE libraries (link).

Do not hesitate to contact us to discuss your own application.

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Published by 32bartkeppens

Sofics provides solutions for the ESD/EOS/EMC robustness of integrated circuits. We have a 20+ years track record, supporting 100+ fabless companies worldwide with on-chip ESD protection and custom/specialty Analog I/O’s and PHY’s. Solutions in CMOS, BCD, FDSOI and FinFET technology are available off-the-shelf Since 2019: Sofics: Responsible for business Development worldwide 2009 - 2019: Sofics: Technical marketing director 2006 - 2009: Sarnoff Europe: Support for business development 2002 - 2006: Sarnoff Europe: Solving ESD related issues for customers worldwide 1996 - 2002: Imec, Belgium: Member technical staff Topics: on-chip ESD protection, ESD analysis, non-volatile memories 1996: Engineering degree in electronics from Groep T, Leuven, Belgium (co-) authored more than 40 peer-reviewed published articles.

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