Space applications require custom I/O and ESD protection solutions. Sofics proprietary ESD technology has been used for a number of aerospace projects. Our engineers delivered custom rad-hard ESD devices for TSMC 28nm, 65nm and 130nm CMOS technologies. The cells enable low power design in an extended temperature range. Different concepts are used to enable cold-spare interfaces. Low voltage triggered solutions are available for protection of thin oxide interface circuits.
Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.
Koen Decock, ESD design specialist at Sofics, made a presentation for a full auditorium, organized by the local IEEE SSCS student chapter in Leuven. He talked about on-chip ESD protection, from the basic concepts to the more advanced applications.
Some applications really need high voltage interfaces and circuits. Think about power management and power conversion chips, automotive electronics for engine control, LCD or OLED display driver chips, motor driver electronics and industrial applications. These high voltage applications require other ESD protection clamps compared to the clamps used for protection of low voltage circuits.
Sofics has been involved in a number of chip projects that require custom ESD clamps for high voltage interfaces.
The 22nm FDX process from GlobalFoundries is a great technology for various applications including low-power IoT on the edge, high-bandwidth 5G mmWave devices and automotive products, Since its market introduction, the SOI process technology receives a lot of attention because it combines unique features in one platform. At the 2021 GTC event, GlobalFoundries said thatContinue reading “Optimized IP for GF’s 22nm FDX technology”
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
What is the right ESD requirement for IoT applications? The internet of Things circuits are used in new environments. It is not possible to use the same reliability approaches for all the different applications. Sofics’ CEO Koen Verhaege presented an overview and different cases.
This article provides information about an SCR based ESD protection clamp for RF circuits validated in TSMC 90nm CMOS technology. The ESD protection clamp described has excellent figures of merit: Due to the low parasitic capacitance, low leakage and high Q-factor the influence on the RF performance is limited.
Every computer chip needs on-chip ESD protection at its interfaces. Integrated circuits have different kinds of interfaces. This article discusses approaches to protect output drivers. This article compares different options for output drivers, focused on the NMOS transistor because that is the most sensitive part and is easily damaged during ESD stress.
Despite the fact that IEC 61000-4-2 is a standard created for system level ESD stress it is frequently used for stand alone integrated circuits. The test approach for chips is not defined nor standardized for this requirement so it is important to have a discussion on the test conditions and acceptance criteria. This article outlines 3 aspects that need to be considered if on-chip ESD protection needs to withstand the IEC 61000-4-2 stress