Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 2)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

Introduction

In the first part (link) of the article we looked at the differences between the process options (FinFET, SOI or bulk CMOS). In this second part we look at the different ESD device concepts (Figure 1) in more detail.

Figure 1: ESD protection schematics for different interface types. This article will compare results about diodes, ggNMOS, SCR and active MOS (BigFET) protection approaches

ESD diode

The simplest ESD device is a diode. The discussion below is based on an Nwell diode. The Pwell diode is similar. Two main types of diodes exist: gated or non-gated. In Figure 2, the performance of the diodes is shown for the three options. The ESD performance is compared in two ways: per diode perimeter (top, left: mA/um) and per area (bottom, left of the figure: mA/um²)

  • In CMOS the non-gated, or STI diode is the most popular, though the gated diode can be used as well.
  • For SOI, the situation is different: if no gate is drawn, the anode and cathode are electrically isolated from each other as STI will be formed in between. To avoid this, the active area needs to be extended, overlapping the well region. This creates DRC violations which are not always accepted by the foundry. From the measurement it is seen that these SOI diodes exhibit an order of magnitude lower failure ESD current compared to bulk diodes. This is caused by the confined volume of the body of the diode, in which heat dissipation is slower and damage occurs more easily. Therefore, some SOI technologies, as the one used in this study, offer the option of etching away the buried oxide below the device. When this is done, one can see the diode performance is restored, and in this case even exceeds the CMOS diode performance.
  • For the 16nm FinFET device, two diodes are shown: A first one uses LV design rules, the second is created with HV design rules. It is clear that the HV diode outperforms the LV design. Per perimeter the difference is much bigger as to the area comparison, as the LV design is smaller for the same perimeter. But in any case, the required area is larger than for the bulk diode. As the wafer cost differs 8% compared to bulk, one could state that the FinFET diode is 50% more expensive for the same failure current level.
Figure 2: Comparison of ESD diodes for the 3 processes. On the left side the comparison is summarized. Top-left shows the performance of the diodes expressed in mA of ESD current per device perimeter (um). Bottom-left introduces the layout area as a parameter by expressing the ESD current capability (mA) per silicon area (um²). The diode of the SOI process (with BOX removed) has the highest performance per area. On the right side the TLP curves are shown for the FinFET diodes. Clearly the high voltage design performs much better compared to the design based on low voltage layout, even when the layout area is considered.

ggNMOS device

To compare ggNMOS devices, we need to take a refresher into ESD physics. It is an NMOS transistor that is turned into a 2-terminal device. The drain is the first terminal, typically connected to the I/O pad. The other terminal connects to the gate, source and substrate and is connected to the Vss supply. Because the gate is tied to the substrate/source the device is turned off. However, there is also a parasitic NPN device inside the transistor (Figure 3).

Figure 3: NMOS transistor cross section (bulk CMOS) and the hidden parasitic NPN transistor. The collector (C) is the drain, emitter (E) is the source and the body is the base (B).

There are different regimes in the device behaviour (Figure 4).

  • For low voltage at the drain, below the breakdown voltage of the drain-substrate junction, the current between the terminals is limited to the junction leakage current.
  • Once the voltage reaches the breakdown voltage of the drain-substrate junction an impact ionization current flows. This grows into an avalanche current when carriers create new electron-hole pairs in the large electric field at the drain (Figure 4, green arrow).
  • The avalanche current flows to the nearest substrate contact if available. A voltage drop builds up over the substrate resistance.
  • When the voltage across the substrate resistance reaches 0.7V the NPN is turned on. The beta multiplication enables a high current from drain to source at a lower electrical field and voltage at the drain. This causes the snapback behaviour. The drain voltage is reduced to the holding or clamping voltage (Figure 4, red arrow).
  • Eventually, at high current, the transistor is burned out (Figure 4, blue arrow).
Figure 4: TLP IV curve for a 3.3V ggNMOS transistor, with 3 main areas of interest. The green arrow depicts the trigger voltage defined by the avalanche breakdown voltage of the drain-substrate junction. The bipolar device is triggered if the base voltage reaches 0.7V. Thanks to the multiplication the NPN can stay on even at a lower drain voltage (red arrow). J.E heating at the drain junction leads to ESD failure/damage of the transistor (blue arrow).

Of course a single NMOS transistor cannot shunt all the ESD current. ESD designers use a multi-finger device layout with e.g. 20 device ‘fingers’ connected in parallel. Typically one finger is triggered into snapback first. In order to trigger all the fingers, the voltage seen by the inactive fingers must be high enough to ensure the drain junctions also start avalanche multiplication. Simply put: the failure current of the first finger (Vt2 – Figure 4, blue arrow) must be higher than the trigger current of the inactive fingers (Vt1 – Figure 4, green arrow). This is achieved by blocking the silicide at the drain. This leads to a higher voltage at the drain that is conducting current. It is called macro-ballasting. There is a second reason for adding the silicide block, which is called micro-ballasting. It spreads the current uniformly over the drain of one finger [12-13]. There is another effect that is important which is bulk coupling [14]. The avalanche current of the different drains add up, such that the field required by each subsequent finger is reduced. The main cause for damage is the heat associated with avalanching. If the field is reduced, the failure current can be improved.

Figure 5: Comparison of TLP curves of I/O NMOS transistors in SOI, Bulk CMOS and FinFET process technology

What does it mean for the different technologies? Figure 5 provides a summary of TLP data for high-voltage I/O NMOS transistors in the 3 process options. Looking at SOI, unless the substrate contact is placed within the source, the impact ionization or avalanching current cannot flow to a bulk contact. The substrate resistance can be regarded as infinite: the parasitic NPN will trigger almost instantly. This leads to a low Vt1, which seems attractive when the device is used as protection device. However, it is detrimental if it is a device that needs protection. The high temperature associated with avalanching cannot be dissipated easily because of the confined volume. And no relief because of bulk coupling is possible: the fingers are electrically isolated. SOI MOS devices are known to be extremely weak for ESD [15].

For FinFET, the confinement of the fingers is somewhat relieved as the narrow body is not shielded from the substrate. Moreover, body coupling is possible. Therefore, the performance is somewhat in between.

Silicon Controlled Rectifier (SCR)

Next up: SCR devices, well known in CMOS [17]. An PNP (p+/nwell/p-substrate) and an NPN (nwell/p-substrate/n+) are coupled in a positive feedback loop, such that high currents can flow with low power dissipation, i.e. at a characteristically low holding voltage of 1.2V. Techniques to avoid latch up with these structures will not be discussed here [16]. More important is how the device can be construed in SOI [18]. First thing to note, as was the case for the diode: if the regions are simply drawn separately, STI will be formed, disabling current flow. Thus, the active area must extend from anode to cathode. The trigger taps (p+ in pwell as G1, and the n+ in nwell as G2) must be reachable as well. Therefore, the anode and cathode need to be drawn in smaller segments, interchanging Anode/G2 in the nwell and Cathode/G1 in the pwell.  Furthermore, silicide block needs to be applied to avoid shorting anode and cathode. A gate stretching from anode to cathode might avoid the DRC horror zone of active-without-implant, it also yields a device with high leakage, caused by parasitic NMOS and PMOS devices.

The SOI-SCR created this way has shown good performance in SOI technologies such as 65nm and 90nm. However in 22nm SOI, the leakage was too high, especially at high temperature, probably due to the extension of the depletion regions. For the given process, the BOX can be etched away however, restoring the performance of SCR’s in bulk technology.

Figure 6: TLP results for Silicon Controlled Rectifier (SCR) devices in SOI technology. The blue curve is for an SOI-SCR. The high holding voltage is related to low bipolar beta’s. Because the SCR is confined by the BOX underneath the device the failure current is rather low. The green curve represents an SCR device where the BOX was removed. This device behaves similar to a bulk-CMOS SCR device.

Explaining the details of the SCR layout in FinFET would lead us too far, as it is dependent on many details of the thousand pages DRC manual, for this purpose it suffices to state it is possible, and performance is more than reasonable (Figure 7) [2].

Figure 7: SCR based power clamp for core domain in a 16nm FinFET technology.

BigFET rail clamp

Lastly one could use the BigFET approach to provide protection between the supply lines. This uses an RC timing circuit to detect ESD. The detection circuit biases the gate of a large (of more than 1000um gate width) MOS device to shunt ESD current. Typical drawbacks are a large silicon footprint, high leakage. On the positive side, the BigFET devices use standard transistors models. This means that they can easily be simulated in Spice. This makes it easy to transfer the approach between technologies: the difference between CMOS, SOI and FinFET is minimal.

Summary

In this article we compared different process options (Bulk CMOS, SOI and FinFET). The intrinsic robustness of the different options is influenced by the device cross sections (First part of the article – Link). In this second part the different ESD device types (Diode, NMOS, SCR and BigFET) were compared in more detail.

Despite obvious issues associated with SOI and FinFET, such as decreasing design windows and lower performance of the ESD clamps, effective protection is possible in any of these nodes. We provide insights to identify the right protection approach in each case.

Contact us for more info

Contact us if you like to discuss the ESD properties of your next chip project on SOI, FinFET, BCD or bulk CMOS.

References

  1. Wafer price for advanced nodes – https://www.techspot.com/news/86813-analysts-believe-single-tsmc-5nm-wafer-costs-17000.html
  2. Van der Borght J, et al., “Local I/O ESD protection for 28Gbps to 112Gbps SerDes interfaces in advanced CMOS and FinFET technology”, 2019 Taiwan ESD and reliability conference (Link)
  3. Keppens B, “ESD relevant issues and solutions for overvoltage tolerant, hot swap, open drain, and failsafe interfaces”, 2011 Taiwan ESD and reliability conference (Link)
  4. C. A. Torres, et al., “Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS Technologies”, Proc. EOS/ESD 2001
  5. S. S. Poon, T. J. Maloney, “New Considerations for MOSFET Power Clamps”, Proc. EOS/ESD 2002
  6. G. Boselli et al., “Analysis of ESD Protection Components in 65nm CMOS: Scaling Perspective and Impact on ESD Design Window”, EOS/ESD Symposium, 2005
  7. T. J. Maloney, N. Khurana, “Transmission Line Pulsing techniques for Circuit Modeling of ESD Phenomena”, Proc. Of the EOS/ESD Symposium 1985
  8. Keppens, Bart, “Contributions to standardization of transmission line pulse testing methodology”, Proc. Of the EOS/ESD Symposium 2001
  9. Barth, John, “TLP Calibration, Correlation, Standards, and New Techniques”, 2002
  10. Backers I, et al., “Novel tool for accurate prediction of the ESD failure voltage of analog circuits”, 2009 IEW ESD workshop (Link)
  11. Sorgeloos B. et al.,“The impact of a decade of Technology downscaling”, 2012 Taiwan ESD and reliability conference (Link)
  12. Verhaege K, et al., “Novel Design of Driver and ESD Transistors with Significantly Reduced Silicon Area”, 2000 EOS/ESD Symposium (Link)
  13. Mergens P.J., et al., “Multi-Finger Turn-on Circuits and Design Techniques for Enhanced ESD Performance and Width-Scaling”, 2001 EOS/ESD Symposium (Link)
  14. Keppens B, et al., “SCR based ESD protection of Output Drivers in EPI technologies avoiding competitive triggering”, 2005 RCJ Symposium (Link)
  15. Keppens B, et al., “Concept for Body Coupling in SOI MOS Transistors to Improve Multi-Finger Triggering”, 2006 EOS/ESD Symposium (Link)
  16. Fukuda Y, et al.,“Solving the problems with traditional Silicon Controlled Rectifier (SCR) approaches for ESD”, 2008 RCJ Symposium (Link)
  17. Avery, L., “Using SCRs as Transient Protection Structures in Integrated Circuits”, EOS/ESD 1983
  18. Marichal, O. et al., “SCR based ESD protection in nanometer SOI technologies”, EOS/ESD 2005 (Link)

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