ESD protection for SOI technology

Silicon On Insulator (SOI) technology has been around for decades but despite several technical advantages (lower power consumption, shorter gate delay, reduced parasitic capacitance) it has not replaced bulk CMOS process technology. For certain applications the benefits can outweigh the higher wafer cost and design challenges like floating body and history effects.

Silicon On Insulator technology has a strong influence on the behavior of conventional concepts for protection against Electro Static Discharge (ESD). This article discusses the challenges and provides examples how these can be solved.

FD-SOI wafer and typical NMOS transistor cross section
(figure from GSA article: https://www.gsaglobal.org/forums/fd-soi-a-technology-setting-new-standards-for-iot-automotive-and-mobile-connectivity-applications/)

ESD challenges

There are several challenges for ESD protection in advanced SOI technology:

  • Similar to advanced CMOS technology on bulk wafers, the available margin in the ESD design windows for core protection is very narrow. The thin gate oxide is damaged if the voltage across, even momentarily (100ns), is higher than 4V – 5V.
  • Due to the thin silicon film the depth of the ESD devices is smaller compared to bulk technology. The junctions are shallower, reducing the volume for heat dissipation. Moreover, the BOX underneath the devices prevents heat transfer to the rest of the wafer. ESD devices in SOI exhibit higher on-resistance for the same silicon area and also fail at lower current levels.
  • MOS transistors are more sensitive compared to their bulk counterparts – see below.

Fortunately SOI technology can provide a number of advantages for custom ESD cells:

  • Because the devices are completely isolated from the bulk/substrate of the wafer, ESD designers can easily stack several devices on top of each other to create protection for high-voltage tolerant interfaces.
  • In bulk CMOS, the parasitic PNP transistor in Nwell diodes creates a path for ESD current into the substrate. When designers use a stack of such diodes, the Darlington effect multiplies the leakage. The ESD current injected in the substrate can cause unwanted turn-on of nearby parasitic devices leading to circuit latch-up. These effects are circumvented in SOI technology.

Conventional ESD protection devices

The article discusses the typical ESD concepts like diodes, snapback and active MOS transistors and their behavior in SOI process technology.

Diode

Diodes are really important building blocks for a full-chip ESD protection approach. IC designers use ESD diodes for several stress combinations.

ESD diodes are typically used for I/O protection (shown here), between VSS and VDD and between different GND nodes.

As mentioned in the introduction, the challenge in SOI technology is to reduce the resistivity in forward mode and to increase the ESD robustness. Because the STI-isolation reaches down to the BOX layer, there are 2 ways to design diodes in SOI technology:

  • Option 1: Blocking the STI-oxide between the N+ and P+ junctions (‘NO-STI’ diode). This means that the active area (OD) layer is also drawn in the area between the anode and cathode regions. The silicide layer must be blocked to prevent short circuit between the 2 highly doped regions. The distance between the 2 junctions must be increased, leading to higher resistance in forward mode.
  • Option 2: Inserting a gate between the 2 junctions (‘Gated’ diode). This creates a more dense layout leading to reduced series resistance in forward conduction. The anode-cathode spacing (LAC) is reduced compared to the first option.

In the figure below the 2 layout options are compared in a 65nm SOI technology.

Comparison of 2 diode layout concepts for a proprietary 65nm SOI technology. The STI isolation must be removed between the anode and cathode. This can be done (left) by extending the active area between the 2 regions or by (right) adding a gate between them. The right option leads to improved ESD performance and lower resistivity.

While it is clear that the gated diode is the best solution for SOI technology it is important to point out that the ESD robustness per perimeter (9mA/um) is much lower (roughly 1/4th) compared to the same device in bulk CMOS (link)

Snapback MOS

The NMOS transistor has been used a lot for ESD protection in mature bulk-CMOS technology. The parasitic bipolar NPN device provides a high ESD robustness per perimeter (10mA/um). However, in thin-film SOI technologies this drops to 1mA/um or less. Moreover, analysis shows a large statistical variation between identical layouts on different dies.

Besides a strongly reduced volume to dissipate the ESD energy, the complete isolation of the NMOS body regions prevents the transfer of NPN base potential to adjacent layout fingers. A detailed discussion can be found in our peer-reviewed paper (link).

Graphical representation of the cross section of NMOS transistors in bulk and SOI processes. In bulk technology (top), the bipolar NPN base (P-bulk) potential from one finger can easily be transferred to the adjacent fingers because all the NPN base regions are created in a shared p-substrate. For thin film SOI processes (bottom), the base regions for each of the parasitic NPN devices are completely isolated from each other.

There is another way to ensure multiple segments of a MOS transistor turn on together during ESD stress events. IC designers can increase the drain area (Drain contact to gate spacing) and remove the silicide. This increases the failure voltage of the NMOS device, ensuring parasitic NPN transistors in adjacent fingers/segments will also turn on. However, this technique increases the required area and parasitic capacitance. In most cases it is better to prevent ESD current through MOS (output driver) devices and use a parallel ESD solution instead.

Active MOS

While it is clear that snapback MOS and diode structures have a much lower performance in SOI technology there are fortunately also ESD concepts that have a similar behavior. Many IC designers and foundries employ so-called BigFET protection (‘rail’) clamps between the power lines. In that case an RC/slew-rate detection circuit (and a few inverters) are used to quickly turn-on a large MOS transistor whenever an ESD event occurs. The ESD robustness per area for such BigFET design is typically lower compared to the snapback MOS robustness in bulk CMOS. In SOI technology the performance is about the same.

During ESD stress, the MOS transistor is used in active mode and can be easily simulated using the Spice models provided by the foundry. There is no need to use silicide block on the drain to enhance multi-finger turn-on. The ESD robustness per area is roughly the same in bulk or SOI process nodes.

Experience from Sofics

Sofics engineers have supported a number of projects on SOI technology, both at foundries as well as on proprietary processes from Integrated Device Manufacturers (IDM).

ApplicationCMOS node
High temperature, high voltage1um
General digital, analog and high temperature130nm (PD)
Wireless LNA130nm (PD)
Computing platform90nm (BST)
High performance computing65nm (PD)
IoT, mmWave, Radar22nm (FDSOI)

Sofics has several solutions for SOI technologies in 3 categories:

  1. Our engineers have build-up specific technical know-how on the (ESD) challenges and solutions for SOI processes like techniques to minimize the required area for ESD protection
  2. Several of Sofics patented solutions are portable to SOI technology like Diode Triggered SCRs (DTSCR)
  3. SOI specific patents like SOI-SCR designs and new ESD robust snapback MOS layouts

Example solutions from Sofics

Improvement of snapback MOS transistors

Our engineers invented a novel way to enhance the ESD robustness of NMOS transistors in SOI technology. As discussed above, the BOX layer prevents bulk-coupling between adjacent fingers. This can be restored with a special layout technique described in the BCMOS patent. In the layout, Source and Drain areas are interrupted with either, P+, an additional gate or just active area without implant.

Layout view (top) and cross sections of different ‘body-coupling’ techniques to connect body regions of adjacent fingers.

In these 3 options a p- tunnel is created between the area under the gate (device body, base of the NPN) of adjacent fingers. The results are stunning: there is a 2x improvement of the ESD performance per area.

2x improvement for snapback NMOS devices with the Sofics’ proprietary body-coupling technique. On the left side the silicide blocked area was optimized. On the right side the BCMOS solution leads to lower trigger voltage and more uniform triggering, in a smaller area.

Enable Silicon Controlled Rectifiers in SOI

IC designers that design on SOI technology are typically happy that they do not have to think about latch-up anymore. In bulk-CMOS and BCD technologies latch-up events can cause a lot of problems and even lead to destruction of silicon chips. However, in SOI technology, the parasitic SCRs (Silicon Controlled Rectifiers) are ruled out.

However, SCR devices can also be used as very efficient ESD clamps, and can be made immune to latch-up. Another key invention from Sofics is to enable the design of SCR clamps in SOI technology. It involves drawing a larger active area (covering the complete SCR device), blocking the silicide layer across lowly doped areas and segmenting the anode/cathode areas to introduce the G1/G2 trigger islands.

Comparison of a 1.0V thin oxide snapback NMOS device and a diode triggered SCR device in SOI technology. The low clamping voltage of the SCR provides additional margin in the ESD design window.

Conclusion

SOI technology introduces several challenges for the ESD designer like narrow ESD design windows, sensitive MOS transistors and higher resistivity due to the thin film. This article provided more background and example data on these issues.

Fortunately, there are several ways to overcome those challenges. Sofics has supported IC companies with novel ESD concepts that improve IC performance and increase the ESD robustness. Various new layout techniques have been developed to enable snapback MOS transistors and silicon controlled rectifiers with low trigger and clamping voltage.

Further reading

  • A comparison between 22nm bulk CMOS, 22nm SOI and 16nm FinFET (link).
  • Technical, peer-reviewed article about the design of Silicon Controlled Rectifiers in SOI technology (link).
  • Technical, peer-reviewed article about the Sofics’ BCMOS solution (link)
  • Press release about a cooperation on the development of a SOI platform (link).
  • Contact us (info@sofics.com) to discuss your next (SOI) IC project.

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Published by 32bartkeppens

Sofics provides solutions for the ESD/EOS/EMC robustness of integrated circuits. We have a 20+ years track record, supporting 100+ fabless companies worldwide with on-chip ESD protection and custom/specialty Analog I/O’s and PHY’s. Solutions in CMOS, BCD, FDSOI and FinFET technology are available off-the-shelf Since 2019: Sofics: Responsible for business Development worldwide 2009 - 2019: Sofics: Technical marketing director 2006 - 2009: Sarnoff Europe: Support for business development 2002 - 2006: Sarnoff Europe: Solving ESD related issues for customers worldwide 1996 - 2002: Imec, Belgium: Member technical staff Topics: on-chip ESD protection, ESD analysis, non-volatile memories 1996: Engineering degree in electronics from Groep T, Leuven, Belgium (co-) authored more than 40 peer-reviewed published articles.

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