ESD clamps for high voltage, BCD processes

In the semiconductor world there has always been a lot of focus on progressing to the next process node. This was Moore’s law: adding more transistors in the same area and increasing the performance of CPU/GPU chips.

To reduce the power consumption, the main supply voltage for logic/digital circuits has been reduced with every node. The I/O voltage range typically followed. In advanced FinFET processes the maximum I/O voltage is reduced from 5V in mature processes to 1.5V or lower. But some applications really need high voltage interfaces and circuits. Think about power management and power conversion chips, automotive electronics for engine control, LCD or OLED display driver chips, motor driver electronics and industrial applications. These high voltage applications require other ESD protection clamps compared to the clamps used for protection of low voltage circuits.

Because the I/O requirements (speed, drive strength, signal levels) are different for each case, foundries typically do not provide I/O circuits for such high voltage interfaces. Sofics has been involved in a number of chip projects that require custom ESD clamps for high voltage interfaces.

ESD concepts used in the industry

Below is an overview of different kinds of ESD devices used for high voltage (HV) or BCD processes. There are clamps that are typically provided by the foundry like zener or PNP based clamps, active RC-MOS/BigFET rail clamps. Some fabs also provide SCR based ESD clamps.

6 different concepts frequently used for ESD protection in high voltage (HV) and BCD process technologies

The ESD clamps with a low clamping voltage, like SCR devices, are frequently used for I/O interfaces that require a high ESD robustness. Some foundries also promote their snapback LD-NMOS devices for ESD protection. For instance output drivers with high drive current are said to be self-protective. That is also convenient for open-drain interfaces. However, at Sofics, we do not recommend it because we have noticed degradation (increased leakage) after repeated ESD stress pulses in snapback NMOS devices in almost every high voltage process (link). When a low clamping voltage is allowed we prefer SCR devices from our TakeCharge portfolio.

On the other hand there are clamps with a high holding voltage like PNP or zener devices. These are used for power/rail clamps because they provide enhanced latch-up immunity. The zener/PNP are straigthforward but typically require a large silicon area, even for regular ESD robustness. Moreover, the trigger and clamping voltage is fixed by the process. It is not possible to change the trigger voltage.

Sofics developed new, smaller device concepts with a tunable triggering and clamping voltage and scaleable ESD robustness. We have bundled these solutions in the PowerQubic portfolio. The layouts are designed in the regular process flow. There is no need for additional masks, implants or process changes.

Sofics’ PowerQubic ESD devices for BCD technologies are highly flexible to be able to meet many different requirements

Example case studies

Several fabless companies have integrated these ESD clamps in their ASICs for automotive, industrial and consumer applications. One of our customers developed an application with a 20V interface and power domain on the TSMC 180nm BCD gen II process. For their chip the customer requested a high ESD robustness of 8kV contact discharge according to the IEC 61000-4-2 standard. The minimum trigger voltage was set 20% higher to ensure the clamp is not triggered during functional operation.

PowerQubic ESD solution for TSMC 180nm BCD gen II for a 20V interface/power domain

Another customer was developing a chip for automotive applications. It included an automotive LIN transceiver. While the LIN bus runs at 12V, devices connected to the LIN bus need to be able to sustain much higher transient voltages (40V). The LIN interface also needs higher ESD protection. For their chip in TSMC 0.25um BCD a PowerQubic device was customized.

Details of the ESD protection solution customized for the LIN transceiver block on TSMC 0.25um BCD

PowerQubic clamps availability

Since 2008, PowerQubic devices have been verified on many process nodes (see below).

  • TSMC
    • 0.35um HV
    • 0.25um BCD generation I and II
    • 180nm BCD generation I, II and III
    • 130nm BCD+
    • 55nm BCD – ongoing
  • UMC: 180nm BCD
  • Tower Semi: 180nm BCD
  • KeyFoundry: 180nm BCD – ongoing
  • IDM/proprietary fabs:
    • 0.35um BCD
    • 0.25um BCD
    • 130nm BCD

Contact us if you want to discuss your application with high signal voltage ESD protection requirements, even if your target process is not listed above. You can find more examples for ESD protection in BCD technology in this presentation.

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Published by 32bartkeppens

Sofics provides solutions for the ESD/EOS/EMC robustness of integrated circuits. We have a 20+ years track record, supporting 100+ fabless companies worldwide with on-chip ESD protection and custom/specialty Analog I/O’s and PHY’s. Solutions in CMOS, BCD, FDSOI and FinFET technology are available off-the-shelf Since 2019: Sofics: Responsible for business Development worldwide 2009 - 2019: Sofics: Technical marketing director 2006 - 2009: Sarnoff Europe: Support for business development 2002 - 2006: Sarnoff Europe: Solving ESD related issues for customers worldwide 1996 - 2002: Imec, Belgium: Member technical staff Topics: on-chip ESD protection, ESD analysis, non-volatile memories 1996: Engineering degree in electronics from Groep T, Leuven, Belgium (co-) authored more than 40 peer-reviewed published articles.

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