Optimized IP for GF’s 22nm FDX technology

The 22nm FDX process from GlobalFoundries is a great technology for various applications including low-power IoT on the edge, high-bandwidth 5G mmWave devices and automotive products, Since its market introduction, the SOI process technology receives a lot of attention because it combines unique features in one platform. At the 2021 GTC event, GlobalFoundries said that “the platform is seeing broad industry acceptance with more than $7.5 Billion in design wins worldwide”.

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A few years ago, on an event at Imec in leuven, Brian Chen from GlobalFoundries summarized the benefits of the process for the different applications.

  • 22FDX is best suited for power optimized, heavily duty-cycled IoT platforms because it combines high-performance compute, ultra-low voltage, ultra-low leakage, power-efficient RF and robust MRAM capabilities
  • The different transistor options enable energy-efficient FEM and transceiver integration for 5G mmWave.
  • He also talked about a next generation automotive radar application with high-resolution imaging quality and built-in intelligence.
  • Brian mentioned that several researchers are using the process for their work on quantum computers. It allows to create isolated quantum dots and the back-gate bias option eases design efforts to maintain perfect operating conditions at very low temperature conditions.

Adaptive Body Bias (ABB)

The 22FDX SOI process is special because it has an option to selectively etch away the buried oxide to create bulk regions (Hybrid). This feature allows to connect (and control) the back-gate of the SOI logic transistors. This way the threshold voltage of the transistors can be changed dynamically. The Adaptive Body Bias (ABB) can be used to ensure all functional blocks are always running in optimized conditions.

The dual gate oxide process has many transistor options including thin oxide, thick oxide, bipolar and LDMOS devices for higher voltages. The last 2 options are created inside a bulk or hybrid area. Designers obviously like the flexibility of the process. The main issue seems to be the design complexity to correctly apply this ABB technique and get the most out of the technology. Of course, the foundry and its partners have developed and verified a complete range of IP blocks to simplify the design work.

IP blocks

GlobalFoundries has a very extensive list (link: partner overview) of IP/EDA/design service partners that provide solutions and support to designers. Foundry customers can license back gate bias generators, memory compilers, temperature sensors, ADC/DAC data converters PLLs, voltage regulators, SerDes, Bluetooth, Wifi and many other re-usable blocks from partners like Verisilicon, Dolphin Design, RacyICS, Rambus, Imagination, Synopsys, Analog Bits, …

Optimized ESD protection and Analog I/Os

Designers can rely on the foundry supported I/O library for the most common chip interfaces. But this free library does not provide satisfactory results for a set of unique interface types. To fill this gap, Sofics verified its ESD clamps and analog I/Os on a dedicated MPW run in the summer of 2019. Our engineers also analyzed the intrinsic ESD properties of the technology to define the failure voltage for the different devices. The test chip included typical SOI ESD devices (link: ESD devices in SOI) and unique devices targeted for this SOI process with hybrid options that allowed creating Silicon Controlled Rectifiers and diodes similar to a bulk CMOS process.

Some of our analysis results.

  • Very narrow ESD design windows (less than 4V) due to low failure voltage of basic transistors in 0.8V, 1.2V and 1.5V domains
  • SOI NMOS transistors (in snapback mode) reach about 2mA/um – that is comparable to other thin film SOI processes.
  • Diodes and SCRs created in hybrid/bulk area reach ESD ESD performance levels that are comparable to advanced bulk-CMOS technology: more than 20mA/um perimeter. On the other hand, an SCR created in the thin film fails at a much lower ESD level (about 7x lower) due to the thin SOI layer.

Sofics ESD technology has been used across 50+ process technologies and was specifically developed to enable easy control of the clamp behaviour during ESD stress. Simple layout variations of the device concepts allow ESD engineers to set the trigger voltage, clamping voltage and failure current (example for Diode Triggered SCR: link). The failure current can be changed by simply increasing the perimeter of the devices. Different proprietary concepts are available to cover different application requirements.

Simplified ESD device IV curve as measured using a TLP system. The most important parameters are ‘Vt1’ trigger voltage, ‘Vh’ clamping voltage, ‘It2’ failure current and ‘Ron’ on-resistance

The Sofics technology provides several benefits and complements the foundry provided general purpose I/O library. These are some of the additional options enabled by Sofics solutions:

  • ESD protection for sensitive thin oxide transistors connected to pads through semi-local and full-local I/O protection.
  • Broader voltage level range even beyond 6V. On the 22FDX technology we also verified a clamp that can be used for 12V interfaces, based on the standard process.
  • Protection for overvoltage-tolerant, fail-safe, hot-swap, cold-spare … interfaces when a diode from I/O to Vdd is not allowed (link: 6 concepts to replace dual diode protection)
  • High-speed interfaces that require low parasitic capacitance ESD protection
  • High-impedance analog interfaces that require ultra-low leakage ESD protection.
Vt1 [V]
Vh [V]
It2 [A]
@ 25°C [A]
@ 125°C [A]
A few examples of ESD protection clamps measured on the ESD test chip. This is a subset of available options. Several other cells are available on request.
The leakage of Sofics ESD solutions is at least 100x lower than the comparable foundry concept

Sofics supported a number of products on the 22FDX technology like low-leakage protection for IoT and Bluetooth applications. We provided support for cold-spare compatible ESD protection for space applications (link) and analog I/Os with higher voltage capability (>5V).

Contact us if you want to discuss ESD protection for your 22nm FDX IC design.

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Published by 32bartkeppens

Sofics provides solutions for the ESD/EOS/EMC robustness of integrated circuits. We have a 20+ years track record, supporting 100+ fabless companies worldwide with on-chip ESD protection and custom/specialty Analog I/O’s and PHY’s. Solutions in CMOS, BCD, FDSOI and FinFET technology are available off-the-shelf Since 2019: Sofics: Responsible for business Development worldwide 2009 - 2019: Sofics: Technical marketing director 2006 - 2009: Sarnoff Europe: Support for business development 2002 - 2006: Sarnoff Europe: Solving ESD related issues for customers worldwide 1996 - 2002: Imec, Belgium: Member technical staff Topics: on-chip ESD protection, ESD analysis, non-volatile memories 1996: Engineering degree in electronics from Groep T, Leuven, Belgium (co-) authored more than 40 peer-reviewed published articles.

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