High performance applications like server CPUs in a datacenter are typically made using the most advanced semiconductor processing technology. The latest process node provides benefits like lower power dissipation, higher transistor density and higher processing speed. However, IC designers developing chips in such advanced processes need to take extra efforts to ensure the chips are protected against Electrostatic Discharge (ESD). ESD remains an important reliability issue for semiconductor companies. ESD events can occur during several stages in the development, assembly and actual use of the ICs.
3 challenges for FinFET designs
Sofics engineers have designed and analyzed ESD test chips across 7 different FinFET process nodes on 2 foundries. Every time a detailed analysis of the process, the conventional ESD protection devices and Sofics proprietary solutions have been carried out. Based on these projects we see 3 main challenges for IC designers in FinFET technology
- Basic building blocks like FinFET transistors are sensitive to ESD stress.
- Traditional or conventional ESD approaches are no longer effective
- The design complexity has increased a lot
1. FinFET transistors are sensitive
To ensure interfaces are effectively protected against ESD stress, designers use the so-called ESD design window. It is an approach that summarizes the requirements for the ESD protection for a specific stress case. In mature process technology from >15 years ago, the ESD design window was very wide. However, in recent, advanced process technology the window is closing. The figure below shows the evolution of the ESD design window (horizontal axis) across technology nodes (vertical axis). In the most advanced FinFET nodes the window is reduced to less than 3V for interfaces built with thin oxide transistors.
The failure voltage (Vmax) of the gate oxide during ESD stress is reduced a lot. In 16nm the maximum voltage is 25% lower compared to 28nm CMOS. In 7nm the difference is even 35%.
2. Conventional ESD concepts are no longer effective
To protect Integrated Circuits against ESD events, IC designers add on-chip ESD clamps. In the chip design industry there are many different concepts. Some of these concepts have been used for decades like the grounded-gate NMOST (ggNMOST). During ESD stress the parasitic bipolar NPN is turned on, providing a low resistive current path from drain to source.
“The grounded-gate NMOST (ggNMOST) isTheo Smedes, Fellow for ESD, Latch-up and EOS within NXP Semiconductors – link.
one of the workhorses in the field of ESD”
Unfortunately, this protection concept is not effective anymore in advanced FinFET technology. Our analysis showed that both core and IO transistors are damaged at the onset of snapback in several FinFET processes. In some cases the removal of silicide on the drain side can enable snapback operation. But the resulting failure current of the parasitic NPN is still very limited.
There is another way to use a MOS transistor with large perimeter (~3000um) as ESD clamp. Some ESD designers use a (dynamic) gate bias during ESD stress to turn on the transistor as shown in the figure below. Thanks to the device scaling the area is actually reasonable. However, the leakage becomes the main bottleneck. In 16nm technology we measured leakage of about 0.5uA at 85°C for a single NMOS based so-called BigFET clamp.
Interface circuits are typically protected using the ‘Dual diode’ concept. Due to scaling the junctions are ever more shallow, leading to a reduced ESD robustness. Compared to 65nm CMOS, dual diode ESD performance in 16nm is already 40% lower for the same diode perimeter.
3. Increased design complexity
Compared to mainstream CMOS technology the design complexity has increased a lot. The number of design rules increased drastically and the design rules themselves are also more complex. Custom layout is more restricted than ever before. On the other hand, the layout aspects of design get more important for predicting actual circuit performance. Designers need more iterations to finalize a circuit. According to IBM (@ISSCC 2020) the design time increased by a factor of 5 from 28nm to 16nm FinFET.
The RC parasitics of interconnects are also causing problems. Patterns at the ‘Local metal’ layers are smaller, leading to higher resistance.
In the past (planar CMOS technology) designers responsible for ESD protection could easily transfer their own clamp solutions from the previous CMOS node to the next one. Due to the increased complexity that transfer takes more time. Some device concepts may no longer function as before or do no longer pass the DRC verification.
Clearly, protecting FinFET IC designs against ESD events is not easy. Moreover, you should consider that the cost of failure is much higher in FinFET technology. A new FinFET mask-set costs a few million dollars. The production cycle is also longer. If an ESD issue causes a re-design the time-to-market will be affected. First-time right design for ESD is very important.
Most foundries provide IO libraries for free. However, for several application types the general purpose I/Os and ESD protection clamps introduce all kinds of limitations. For instance the leakage of such GPIO’s can be very high, preventing people to develop e.g. low-power Edge-AI applications. Another typical limitation is the voltage range. Some applications require 3.3V or 5V interfaces. However, in very advanced FinFET technology the IO voltage is limited to 2.5V or even 1.8V. For high-speed digital interfaces the parasitic capacitance of the (analog) IO cells can cause problems with signal integrity.
Silicon and product proven ESD solutions
Sofics has developed proven ESD-IP for the major FinFET processes. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. Contact us to discuss how our proven solutions can protect your FinFET project.
Sign-up to receive more articles from our monthly pulse.