Semiconductor companies using 2.5D and 3D hybrid integration need to consider Electrostatic Discharge (ESD) protection early in the design, even for die-2-die interfaces that remain inside the package. There are several challenges but also opportunities. The use of a local ESD protection clamp at the TSV offers more robustness, higher performance, more flexibility, all in a strongly reduced silicon footprint.

The Sofics abstract was accepted for publication and presentation at the 2021 Taiwan ESD and Reliability conference. Due to covid19 travel restrictions the presentation was pre-recorded. The video is available below.

The slides can be browsed in the article below. The paper can be downloaded here.

Introduction

A growing number of semiconductor applications are turning to 2.5D and 3D integration for various reasons. Integrating multiple dies in a single package can provide several benefits.

  • Reduce total power consumption
  • Reduce PCB area and volume
  • Enhance performance (e.g. faster compute to memory links)
  • Speed up development cycles
  • More robust against copying by competitors
  • Select most optimcal process technology for each feature

ESD discussion

In 2.5D and 3D integrated packages there are 2 different interfaces.

  • Interfaces that connect outside of the package
  • Die-2-die interfaces that remain inside the package.

There is a clear difference between these 2 types for the relevant ESD requirement, the signal voltage and layout of I/O circuits and ESD devices. IC designers that use customized ESD cells can enjoy several benefits.

Sofics experience

Sofics has supported a number of hybrid integration projects. The technology is easily adapted to match requirements. Several customers have used the local ESD protection clamps for their products. The presentation focused on low-cap ESD cells for high-speed die-2-die interfaces in FinFET technologies.

Awarded presentation!

The event was organized in a hybrid way. International presenters could not join in-person due to the travel restrictions in Taiwan. Fortunately, after the (recorded) presentation there was an opportunity to remotely discuss questions from the audience through a zoom call with the conference room. Plenty of relevant questions were discussed.

After the event the Sofics paper received the best presentation award.

4 responses to “Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration”

  1. […] transistors in advanced CMOS and FinFET processes. Several cases studies can be found here (link, link). The local clamp approach provides most flexibility to fine-tune the protection for each […]

  2. […] Conventional ESD concepts, provided by most foundries, are suited for an entire I/O ring. However for 3D stacked assemblies, IC designers use small I/O segments scattered around the die, each segment close to the Through Silicon Via (TSV). An approach with local I/O clamps provides much more flexibility (link). […]

  3. […] are the guidelines we have used for our customers when they asked us to design for e.g. 100V HBM (examples). It is possible, maybe even likely, those are an […]

  4. […] the most sensitive interface circuits. You can read more about it in several articles (link, link, link, link). The use of proprietary Silicon Controlled Rectifier (SCR) devices strongly reduced […]

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