ESD protection solutions for space applications

For the 2021 TSMC OIP event, Sofics prepared an overview about Space electronics. Chips used in space require custom ESD protection and I/Os.

Video recording for the 2021 TSMC OIP event.

The video recording is available above. Moreover, you can also browse the slides below.

Introduction

Space applications capture a lot of attention lately. In the past, space exploration was limited to national space agencies but now also commercial companies are getting onboard.

Like any smart device on earth, devices sent beyond the 80 km limit all include a lot of electronics.

It is important to understand that it is not straightforward to send conventional electronics into or beyond orbit. IC designers need to consider the harsh environment.

There are 4 key issues that influence the ESD design process:

  • Need for low power solutions
  • Extended temperature range
  • Radiation hard requirements
  • Cold-spare interfaces

Low power requirements

Frequently space applications need to harvest energy from the sun with solar panels. The engineers also have to consider that the solar panels are not always active. When the device is far away from the sun or in the shadow of a planet or moon, a battery takes over.

It is clear that this limits the total available energy for the electronic circuits. IC designers use low-power designs and rely on techniques to shut-down parts of the circuit when these are not relevant.

In large logic chips the leakage of the I/O cells is only a small fraction of the total IC leakage but any improvement should be investigated.

If you think about satellites orbiting the earth, it is easy to see that there is a big temperature difference between when the satellite is in the shadow of the earth and when it is in direct sunlight. A difference between cold/hot can be 300°C or more. The temperature fluctuations are causing issues for chip packages. The electronic circuits inside the package must be able to handle this large temperature range too. ESD devices typically have a much higher leakage at high temperature. Another reason why IC designers should select low-leakage ESD concepts.

Extreme radiation

The enhanced radiation can degrade circuit performance or even damage some circuits for instance during single-event-latch-up.

Radiation can alter the contents of memory blocks, causing it to misbehave. Radiation can degrade the performance when charges are trapped inside oxide layers in the integrated circuits. These trapped charges can for instance drastically change the Vth level of MOS transistors. This could lead to increased leakage or lock the transistor in one mode (open/closed).

Frequently thick-oxide transistors are more vulnerable for total dose irradiation because that oxide has a higher defect density and thus more easily traps charges. Unfortunately, conventional I/O libraries and ESD protection clamps built with thick-oxide transistors.

Cold-spare interfaces

IC designers in space applications frequently use a back-up circuit when the main/primary circuit fails: a so-called “cold-spare”. A spare or 2nd circuit that is not powered, hence cold.

It is common practice to route the I/O signals to both primary and back-up circuits and only provide a switch for the power to select between the primary and the back-up circuit. This has an important consequence for the I/O pads. The conventional dual diode ESD protection cannot be used for cold-spare interfaces.

Example solutions and conclusions

Sofics proprietary ESD technology has been used for a number of aerospace projects. Our engineers delivered custom rad-hard ESD devices for TSMC 28nm, 65nm and 130nm CMOS technologies. The cells enable low power design in an extended temperature range. Different concepts are used to enable cold-spare interfaces. Low voltage triggered solutions are available for protection of thin oxide interface circuits.

Contact us to discuss your (space) application.


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Published by Bart Keppens

Chief Business Development at www.sofics.com Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog IOs and on-chip ESD protection. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. Our technology has been characterized on 11 foundries including advanced nodes at TSMC, UMC, GF, Samsung Foundry.

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