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ESD clamp inserted at the IO
Optimized on-chip ESD protection to enable high-speed Ethernet in cars.
Introduction: ESD protection concepts for I/Os
Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
Applying System level ESD (IEC 61000-4-2) stress on ICs
ESD protection for 2.5D and 3D packages
ESD protection of interfaces with thin gate oxide transistors
6 concepts to replace dual diode ESD protection
Local ESD protection in analog IOs
Diode triggered SCRs for ESD protection in CMOS ICs (part 1)
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