Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes

Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions. We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.

In Q4 2020 a close cooperation between Samsung Foundry and Sofics started. Sofics proprietary ESD protection clamps have been included on various test chips on the most advanced FinFET technologies including 4LPP, 5LPE and 8LPP processes.

One of Sofics ESD and FinFET experts, Johan Van der Borght, presented the first analysis results during the Samsung Foundry SAFE event in November 2021.

Video recording of the presentation from Johan Van der Borght at the 2021 Samsung SAFE event

Introduction

On-chip ESD protection clamps are required to protect sensitve circuits and to ensure high yield during production and assembly. Traditionally IC designers use a combination of RC-based railclamps between power and ground lines and dual diode based protection for interfaces. However, this conventional approach is not optimized for FinFET circuits. For sensitive thin oxide interfaces that traditional approach is no longer effective.

ESD protection for Samsung Foundry 4LPP

For interface protection it is clear that the conventional dual diode based approach does not work anymore. Fortunately there are other solutions. In our cooperation with Samsung Foundry proprietary ESD clamps are verified on silicon. Several devices based on Silicon Controlled Rectifiers (SCR) have been analyzed for the 1.2V core and 1.8V I/O domain in 4LPP technology.

Sofics has developed ESD clamps that can be used locally, in the I/O area. Johan presented examples for 1.2V and 1.8V interfaces. The Sofics SCR solutions can be easily adapted to several cases. Unlike conventional ggNMOS based protection, the trigger and clamping voltage can be defined by layout changes. There is no need for an additional ESD implant mask or process step. Despite a snapback operation the SCR devices trigger across multiple fingers. This means that the ESD robustness level is correlated to the total device perimeter.

ESD protection for Samsung Foundry 8LPP, SerDes circuits

The first part of the cooperation with Samsung Foundry focussed on the protection of a high-speed SerDes circuit on 8LPP technology. Without prior silicon results for the Sofics SCR devices on the technology a nice result was achieved.

Conclusion

On-chip ESD protection for advanced FinFET processes is challenging. Johan demonstrated in several cases on 4LPP and 8LPP technology that the Sofics proprietary solutions can provide benefits including small area, low leakage and low parasitic capacitance.

We are delighted that our first cooperation with Samsung Foundry is just the start. Testchips are designed on additional FinFET process nodes in the following quarters.

The proven ESD clamps will be included in the Samsung Foundry FinFET PDKs. This will greatly lower the threshold for fabless companies to use Sofics technology on Samsung Foundry designs.

Contact us if you like to get more details about our solutions.


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Published by Bart Keppens

Chief Business Development at www.sofics.com Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog IOs and on-chip ESD protection. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. Our technology has been characterized on 11 foundries including advanced nodes at TSMC, UMC, GF, Samsung Foundry.

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